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The AND/OR and Inverter Structure

Creating "AND" and "OR" structures using MOSFET transistors is easily accomplished by placing the nmos and pmos transistors either in series (AND) or parallel (OR) as shown in Fig. 2 and 3. Shown in Fig. 2 (a) and (b) are two MOSFET transistors connected in series. The singular current path in both structures defines the "AND" operation. Shown in Fig. 3 (a) and (b) are two MOSFET transistors connected in parallel. The parallel current paths represent the "OR" structure.

Figure 4 shows an nmos "AND" structure with the source of M1 connected to ground (MOSFET Rule #2). An nmos switch is turned-on when a logic high is applied to the gate input. The logic expression for the circuit shown in Fig. 4 is meaning that the output F is low if A and B are high. This is called the analogous structure. If gate inputs A and B are a logic high, then the output node of the "AND" structure will be connected to ground (a logic low). If either input A or B is a logic low then there will not be a path to ground since both MOSFET transistors will not be turned-on. In CMOS technology, a complementary transistor structure is required to connect the output node to the opposite power supply rail. The expression and transistor configuration for the complementary structure is obtained by applying DeMorgan's theorem. A method for creating the full CMOS transistor structure is described in part IV.

Fig. 4 An nmos Transistor Structure Realizing the expression F = (A B)_-L

Creating a CMOS inverter requires only one pmos and one nmos transistor. The nmos transistor provides the switch connection to ground when the input is a logic high while the pmos device provides the connection to the V_DD power supply rail when the input to the inverter circuit is a logic low. This is consistent with MOSFET Rule #2. The transistor configuration for a CMOS inverter is shown in Fig. 5.

Fig. 5 The transistor view of a CMOS Inverter

The following design process [1] provides a method for obtaining an optimal CMOS combinational transistor structure given a functional (Boolean) expression. The method is based on the use of mixed logic concepts. The input variables should have a designated assertion level (i.e. Assert Low or Assert High).

In CMOS designs, two transistor structures (one pmos and one nmos) are required for implementing the functional expression. In logic systems, the analogous expression defines what is required to generate the required output assertion level. The complementary expression, obtained by applying DeMorgan's theorem to the functional expression, defines the complementary structure. These two expressions, the analogous and the complementary, are then used to create the transistor network for a CMOS circuit. The design procedure is described as follows in five steps.

1. Identify the "most common" input level by examination of the input assertion levels. This requires that the input assertion levels be defined. An input variable containing a conflict is treated as if it has the opposite assertion level. The "most common" input level will be either "Low" or "High". This is determined by counting the number of asserted high or asserted low inputs after adjusting for conflicted inputs.

2. The "most common" input level is used to specify the type of transistors used for implementing the analogous structure

3. If there is not a "most common" input level then select the input level to be the opposite level of the required output assertion level.

4.(a) Create the analogous transistor structure directly from the functional logic expression. Use the transistor type specified in part 2 for creating the structure.

4.(b)The complementary structure is created by applying DeMorgan's theorem to the analogous expression. The transistor type is opposite to that used in part 4(a).

5. Assemble the analogous and complementary structures to create the full CMOS equivalent circuit. In some cases, an inverter must be added to the output of the circuit to correct the output assertion level.

Example 1:

Given . Both inputs A and B are defined to assert High while the output is defined to assert low. This expression reads the output is asserted low when inputs A and B are both asserted. [Step 1] Determine the most common input level. Inputs A and B both assert high and neither input has a conflict therefore the "most common" input level is High. [Step 2] NMOS transistors are to be used to create the analogous structure. Notice that this is an "AND" type structure. The nmos transistors are connected in series to ground as shown in Fig. 6(a). [Step 4] Applying DeMorgan's theorem to the functional expression yields . In this case, pmos transistors are used to create the complementary structure. The pmos complementary circuit is an "OR" structure with the pmos transistors providing the switch connection to the V_DD. rail. The complementary structure is shown in Fig. 6(b). [Step 5] The completed CMOS circuit is shown in Fig. 7. The output assertion level (low) is correct.

Example 2:

Given: . Inputs A and B are defined to assert high and the output is defined to assert high. This expression reads the output is asserted high when both inputs A and B are asserted. [Step 1] Determine the most common input level. Inputs A and B both assert high and neither input has a conflict therefore the "most common" input level is High. [Step 2] NMOS transistors are to be used to create the analogous structure. Notice that this is an "AND" type structure. The nmos transistors are connected in series to ground as shown in Fig. 8(a). [Step 4] Applying DeMorgan's theorem to the functional expression yields . In this case, pmos transistors are used to create the complementary structure. The pmos complementary circuit is an "OR" structure with the pmos transistors providing the switch connection to the V_DD. rail. The complementary structure is shown in Fig. 8(b). [Step 5] The output assertion level must be corrected by adding an inverter to the output. The completed CMOS circuit is shown in Fig. 9.

The procedures and results for creating the transistor equivalent circuits in Example 1 and Example 2 are the same except that the circuit in Example 2 required the placement of an inverter on the output to correct the assertion level to match desaign specifications. The logic circuit created in Example 1 is commonly called a Positive Logic NAND gate. The logic circuit created in Example 2 is commonly called a Positive Logic AND gate. This procedure can be easily applied to create NOR, OR, XOR, XNOR gates

Example 3:

Given: . Inputs A and C are defined to assert high and input B is defined to assert low. The output is defined to assert high. This expression reads: the output is asserted high when inputs A "OR" B are asserted AND C is not asserted. [Step 1] Determine the most common input level. Inputs A and C both assert high. Input C is conflicted therefore for the purpose of determining the most common input level, C is treated as a low input. Input B is defined to be asserted low and does not contain a conflict therefore the "most common" input level is LOW. [Step 2] PMOS transistors are to be used to create the analogous structure. Notice that the analogous structure contains both an "AND" and "OR" structure. The pmos transistors are connected to the V_DD rail as shown in Fig. 10(a). Input A is defined to be asserted high and a pmos device requires an asserted low input signal therefore the assertion level of A is change to a low to avoid a conflict. This is consistent with mixed logic methods [2] [Step 4] Applying DeMorgan's theorem to the functional expression yields . In this case, nmos transistors are used to create the complementary structure. The nmos complementary circuit contains both an "AND" and "OR" structure with the nmos transistors providing the switch connection to the ground rail. The complementary structure is shown in Fig. 10(b). [Step 5] The output assertion level will be high when the required input assertion levels are met. An inverter on the output is not required. The completed CMOS circuit is shown in Fig. 11.