Leveraging its experience in design verification, and domain knowledge of various technologies like PCI, SONET, Ethernet and Fiber Channel etc., Thinklake is actively involved in development of reusable verification components.

Our vast experience in verification includes:

• Expertise in HDLs, Verilog and VHDL, verification languages, HVLs, SystemC, and verification tools like Specman
• Full chip verification including IP Cores, automated test benches & regression environment
• Development of regression suites in SystemC, ”e”, C/C++, Vera, Perl and Shell scripts, and PLI based verification
• Bus functional models, Protocol monitors and checkers
• Developing automated test benches to create functional and timing verification environment
• Functional and Code coverage analysis

Our team includes highly skilled and experienced engineers who are provided to help develop total verification environment in SystemC. We bring proper resources & methodology (manpower & tool infrastructure) at various stages of the project for:

• Common verification platform for functional, system level, performance, system software, embedded systems, FPGA, & reference board verification
• System modeling & verification in SystemC (to identify performance and architectural integration problems, at a very early stage)
• Functional verification through assertion, directed and, random tests
• System software or embedded software development & verification
• FPGA, reference board development & verification

Our resources provide our customers the ability to hire experienced design verification engineers when they need, based on their project development needs.