This section contains all the projects that I have done during my masters at The University of Toledo. I have done interesting projects in Layout design, circuit design, Logic Design, VHDL descriptions and FPGA implementation of VHDL models. Each project is posted on a seperate page. VHDL source code and simulation results are shown for the projects which need VHDL descriptions. If you have any questions, feel free to contact me. I'll be happy to answer you. All the work shown here is solely done by me. The material here is protected by copy right. If someone wants to copy something from here, please e-mail me at gkjandhyala@hotmail.com.