Figure 4.23. There are two sets of terminals, two inputs on the left and two outputs on the right. In addition there is a fifth terminal labeled control voltage input. The lower left and lower right terminals are grounded. The upper input terminal connects to the source of an N channel enhancement mode MOSFET, and also to the source of a P channel enhancement mode MOSFET. The drain connections of the two FETs are connected together and go to the upper output terminal. The control voltage terminal connects to the gate of the N channel FET. It also goes to the input of an inverter which is described as a triangle with a circle on its nose, see text. The output of the inverter goes to the gate of the P channel FET. End verbal description.