Figure 4.22. There are two sets of terminals, two inputs on the left and two outputs on the right. In addition there is a fifth terminal labeled control voltage input. The lower left and lower right terminals are grounded. The upper input terminal connects to the source of a junction N channel FET. The source connects through a 100 k ohm resistor to the gate. The upper output terminal connects to the drain of the JFET. The control voltage terminal connects to the cathode of a diode. The anode connects to the gate of the FET. End verbal description.