This page shows the progress of Verilog FAQ through different versions. 

Version 09/15:     09/15/2005
This is the current version. 

1. Verilog history updated to include links to System Verilog
2. Conferences and Paper contests section updated.
3. Website links cleaned up.
4. Link to ISD magazine archives and Chip design magazine added.

Version 10.03:     09/29/2003

1. Conference Proceedings archive section added in Part 1
2. GPL CVer added in Free Verilog Tools section in added in Part 1.
3. Links to two free Wave form viewers for Icarus added in Part 1.
4. Free Verilog Code coverage tool section added in Part 1
5. Free Verilog Obfuscator added in Part 1
6. Magma's Blast Create added in Synthesis tools in Part 2

Version 10.02:     11/06/2002

1. Verilog to C/C++/SystemC Converter list updated in Part 3.
2. Free Verilog to C++ / System C Translator added in Part 1.
3. Conferences and Paper contests updated in Part 1.
4. A new section on "Connecting other scripting languages to Verilog" added in Part2 
5. Books and Reference material on Verilog in Part 1 updated with J.M. Lee's book.
6. A new section on VCD (Value Change Data) added in technical section of FAQ Part 2.

Version 10.01:     10/11/2002

1. Surendra Anubolu's ASICDesign Info page added on Links page.
2. Online simulator added in free simulators page.
3. Verilog BNF link added to Part 1.
4. Technical question on compiling files from Emacs added in Techical QA page.

Version 10.00:     03/21/2002

1. Obsolete links removed. many links cleaned up.
2. Ben Cohen's new book added in list of Verilog Books.
3. CVer of Pragmatic-C added in the list of free Verilog Simulators.

Version 9.13:     06/09/2001

1. Many web sites added in "Participating in discussions on comp.lang.verilog" in Part 1.

2. Google Search Engine Added.

3. Source Navigator for Verilog added in "Editors which support Verilog" section in Part 1.

4. Icarus, Ver,  VBS and old Veriwell (Linux) simulators added in the list of "Free Verilog Simulators" in Part 1.

5. Link to "Micron Memory Models" in Part 3 corrected.

6. Comit System's Reference card added in "Free Verilog quick reference card" in Part 1.

7. CynApps product Cynchronizer added in "Verilog to C Converters" in Part 3.

8. CynApps product Cynthesizer added in "C/C++ to Verilog Converters" in Part 3.

Version 9.12:     04/07/2001

1. Dolphin Integration's SMASH simulator added in the list of simulators in Part-3.

2. Free Timing Analyser added in Free Stuff section in Part1.

3. Free VHDL to Verilog Translator added in Free Stuff in Part1.

4. Usenet Information updated in Part1.

5. Conferences and Paper contests updated in Part1.

6. Simpod added in the list of commercial model providers in Part3

Version 9.11:     01/01/2001

1. Main site moved to http://www.bawankule.com/verilogfaq

2. All broken links fixed.

3. nLint from Novas added to Lint tools in Part 3.

4. javapli added in PLI section in Part 2.

Version 9.10:          10/26/2000

1. "Conferences and Paper contests" section in Part 1 updated. 

2. "Future of Verilog" section in part 2 updated with examples of Verilog-AMS.

3. "Verilog to C converter" added in Part 3.

4. Many outdated links fixed in FAQ.

Version 9.9:          05/19/00

1. "Future of Verilog" section in Part 2 updated. Stuart Sutherland's paper on Verilog-2000 added.

2. "Books on HDL Verification" section in Part 1 updated. Principles of Verifiable RTL Design by Lionel Bening and Harry Foster added.

3. "Programming Language Interface" section in Part 2 updated. Stuart Sutherlands book added in the list.

4. "Good Books on Synthesis" section updated with images and correct prices.

Version 9.8:          02/23/00

1. "Conferences and Paper contests " section added in Part 1 updated.

2. VCD Waveform viewer added in "Free Simulation Waveform Viewer" section in part 1.

3. A new section "Free Verilog Design Rule Checker" added in part 1.

4. A new "Free Verilog LRM" section added in part 1.

5. On-line Verilog HDL Quick Reference Guide by Stuart Sutherland added in "Free Verilog quick reference card" section in Part 1.

6. "Verilog Static Checking Tools" section in part 3 updated with Surelint, ReviewVer and Spyglass tools.

Version 9.7:          01/25/00
This is the current version. 

1. "Books on HDL Verification" section added in Part 1. Janick Bergeron's Book added in the section.

2. FTL Systems added in "VHDL to Verilog converters" section in Part 3.

Version 9.6:          12/10/99

1. "Editors which support Verilog " section in Part1 is updated with Prism Editor.

2. "Verilog Code Coverage Tools" section is added in Part 3.

3. Link to Asynchronous Logic page added in Links page.

Version 9.5:          11/12/99

1. "Verilog to HTML converter" section in Part1 is updated with changed link.

2. A new section "Synthesis Standards Working group working on Synthesis" is added in Part 2.

Version 9.4:          10/15/99
This is the current version. 

1. A new "Technical Questions" section in Part2. A separate page is created for these questions and answers.

   • How to model large amount of memory without using too much simulation memory space?

   • How to model Transport and Inertial Delays in Verilog?

   • How to display the system date in $display or $write?

   • How to display bold characters?

2. A new "Visual Verilog  tools " section added in Part3.

3. Prof. Don Thomas's slides on Verilog added in "Free Verilog Tutorials" section in Part1.

4. Michael D. Ciletti's book added in "Books and Reference material on Verilog" in part1. 

5. Link to HierAssist tool added in "Editors which support Verilog" section in part1.

Version 9.3:          09/15/99

1. "Conferences and Paper Contest" section in Part1 is updated. 

2. "Free Verilog Tutorials" section in Part1 is updated. 

3. "Synthesis Tools" section added in Part2.

4. "Simulators" Section updated with InnoLogic System's ESP Symbolic Simulator.

5. A new Search engine added on FAQ main page.

Version 9.2:          08/15/99

1. Information on Superlog added in "Future of Verilog" section. 

2. A new section on "Timing Diagram Designers" added. 

3. A new section "Editors which support Verilog" added. 

4. A new section on "Verilog Static Checking Tools" added. 

5. A new subsection on "Usenet group related to synthesis" added. 

Version 9.1:          07/18/99

1. Bob Zeidman's  "Verilog Designer's Library" added to list of books. 

2. Lycos's usenet site added in the list. 

Version 9.0:          06/06/99

1. C to verilog Converter added. 

2. Micron memory simulation models added in Verilog Model examples. 

3. A new section on Synthesis added. 

   • Synthesis Flow Diagram 

   • Simple example 

   • Unsupported Verilog Language Constructs 

   • Good books on Synthesis

     
      

4. Programming Language Interface section is updated. Information on Swapnajit Mittra's book is added. 

5. EDA Industry Working Groups added. 

6. 3 new links added in Verilog / EDA Links Page 

Version 8.3:          05/12/99

1. Links checked and corrected. 

2. Links to PDF documents changed. 

Version 8.2:          03/04/99
New items

1. Examples from "The Verilog Hardware Description Language" by D.E. Thomas and P.R. Moorby  are added. 

2. Verilog / EDA Benchmarks are added. 

Version 8.1:          01/14/99
Updated items

1. SynpatiCAD's VeriLogger added in Free and commercial simulators list. 

2. SynpatiCAD's Waveformer Pro added in free and commercial waveform viewer list. 

3. Links for VCS updated. 

Version 8:  12/15/98
New Items

1. List of two free verilog tutorials added. 

2. List of Verilog / EDA related conferences added. 

3. FSM Design and Analysis tools section added. Links to Cisco FSM and FSM Designer added. 

Updated items

1. FAQ page moved to Angelfire site. HTML is cleaned up. 

2. Information on SMASH mixed signal simulator added. 

3. Information on J. Bhasker's "Verilog HDL Synthesis, A Practical Primer" added in list of books. 

4. Qualis quick reference card added in the list of free cards. 

5. Links for Analog Verilog and PLI updated. 

Version 7:                08/01/1998

1. Thorough change in look and feel of web pages. 

2. Breakup of one single FAQ page into logical three pages. 

3. Reorganization of information in three sections. 

4. "What's New" page is added to indicate version history. 

5. Verilog parser contributed by Coy Toavs added. 

6. Link to Veripool (public domain Verilog resources) added. 

7. Examples of simple Verilog models added in technical section. 

8. Links to various companies providing Verilog models added in Tools and services section. 

Version 6.1               04/27/1998 

1. Information about Verilog-AMS (Analog and Mixed Signal) added 

2. Information about free PC simulators modified. 

Version 6.0   04/11/1998 

1. Links to Verilog Emacs mode is modified. 

2. Information on Verilog text file to HTML conversion is added. 

Version 5.0   10/26/1997

1. Link to Verilog mode for Emacs added. 

2. Fix for printing Rajeev Madhavan's Verilog quick reference card added. 

3. Comit System's Verilog quick reference card added. 

4. Link to EDN in EDA related magazines added. 

5. Avanti's name in Simulator companies list added. 

6. Absolete comparisons between simulators removed.  

Version 4.0   07/01/1997 

New Items

1. Verilog Preprocessor link 

2. Efficient State machine design  

Updated items

1.  PLI : Swapnajit Mittra's site added. 

2.  Books : James Lee's book added in the list. 

Version 3.0   06/04/1997 

1. A new "Technical Topics" section. This time information about state machine design is added. 

2. Book section is modified. J. Bhasker's new book is added  in the list. 

Version 2.0   03/30/1997 

It contains major additions of topics like

1. List of companies making Verilog simulators. 

2. Different types of simulators 

3. VHDL to Verilog converter  

Following topics are updated.

1.  PLI 

2.  Related web sites  

Version 1.0   02/27/1997 

1. The first version released based on old FAQ.