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Verilog FAQ      Version 09/05: September 2005

FAQ Main  |  Part-1  |  Part-2 Part-3  |  What' New  |   Links    ]


Part 1:

Introduction :

What is Verilog? 
A brief history New
Participating in discussions on comp.lang.verilog 
EDA Industry Working Groups 
Conference Proceedings archive 

General Topics:

Verilog BNF  
Editors which support Verilog 
Verilog to HTML converter 
vgrind def file
Verilog / ASIC / EDA related magazines 
Related Web sites
Conferences and Paper contests   
Books and Reference material on Verilog
Books on HDL Verification 


Free Stuff :

Free Verilog simulators
Free Simulation Waveform Viewer 
Free Verilog Design Rule Checker (Lint)
Free Timing Analyzer

Free VHDL to Verilog Translator

Free Verilog to C++ / System C Translator  
Free Verilog Code Coverage Tool  
Free Verilog LRM 
Free Verilog quick reference card
Free Verilog Tutorials

Free Verilog Obfuscator  
Public domain Verilog preprocessor on web 

Introduction :

 What is Verilog?

Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 50,000 active designers. 

A brief history 

Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway  Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu  Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil   Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally  acquired by Cadence Design Systems, San Jose, CA in 1989. 

Verilog was invented as simulation language. Use of Verilog for synthesis was a complete  afterthought 

Cadence Design Systems decided to open the language to the public in 1990, and thus OVI  (Open Verilog International) was born. Till that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog  simulators. The first of these came to market in 1992, and now there are mature Verilog  simulators available from several sources. 

As a result, the Verilog market has grown substantially. The market for Verilog related tools in  1994 was well over $75m, making it the most commercially significant hardware description language on the market. 

An IEEE working group was established in 1993 under the Design Automation Sub-Committee  to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.

The Verilog Standard was revised in 2001 and it became IEEE Standard 1364-2001

Verilog is evolutionary language. It is growing to cater needs of system designers, verification engineers too. Extensions to existing Verilog language are proposed by Accelera. Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International.
Visit Accelera site to download System Verilog 3.1a LRM.


comp.lang.verilog is an unmoderated newsgroup which passed its vote for creation by 332:9 as reported in news.announce.newgroups on 12 Dec 1991. The charter, culled from the call for votes:

The USENET group is intended at providing a forum for the discussion of topics specific to  Verilog, PLI (programming language interface), SDF (Standard delay file format), Synthesis guidelines, compliance and Verilog modeling. It will also provide users with an ability to share  Verilog/PLI utilities. Users can also use the forum to discuss any Verilog related issues proposed by Open Verilog International and its organizational and technical committees. 

Participating in discussions on comp.lang.verilog

- Deja News used to provide free usenet. Now it is bought by Google and new incarnation is available at

Link to comp.lang.verilog is at hl=en&lr=&safe=off&group=comp.lang.verilog
You can read as well as post the messages.

- You can provide your email address to get postings sent to your email address.

- Your own ISP. Most ISP (Internet service providers) provide news service. You can configure your Netscape, Outlook express or other news readers like Forte Agent to
read available news groups available with the server.

EDA Industry Working Groups

The archives and more information about the Electronic Design Automation (EDA) and Electronic Computer Aided Design (ECAD) related Industry working groups is kept at

Some relevant groups are

Conference Proceedings archives

Archive of proceeding from various conferences like DAC, FPGA conferences is kep here.

General Topics:

Verilog BNF

Verilog BNF lists the formal syntax of Verilog language as defined in Verilog Language Reference Manual.

Editors which support Verilog
  1. GNU Xemacs: It is available from GNU Emacs on Windows NT and Windows 95/98


    Use Emacs / Xemacs with Verilog mode. Michael McNamara , President, Surefire Verification Inc. maintains Verilog Mode for emacs. You can download it from its own web page
    It has installation guide on the page. If you have any problems with the file, you can submit a bug report by sending mail to

  3. Source Navigator for Verilog: Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many verilog files. It parses verilog code into a database that can be used to navigate files, trace connectivity, and find modules and signals in the design. It can even parse your files as you edit so you don't launch those long compile scripts only to end up with a syntax error after 5 minues of compiling.
    Downloads are available for Solaris and Linux.
    More Information :
    Downloads :

  4. The Prism Editor:  is an 'environmentally friendly' editor designed for Windows NT/95/98. No matter what type of files you edit on a daily basis, the editor can incorporate them into a productive system. 

  5. This Shareware editor is available with extensions for Verilog, VHDL, C, ABEL, PALASM, HTML, Synopsys Script File, Synplify TCL, UCF, Synopsys Log File and Error files
  6. Use Crisp editor with verilog tags and print from it. More info / downloads are available from

  8. Use vim (vi improved).  xvim is its GUI version. Download from It supports almost every verilog simulation platform, such as Linux, Solaris, Hp, Sun OS, and Windows.

  10. ed from GetSoft 

For pretty printing one can use above mentioned editors or 

  1. standalone a2ps with Verilog extension. You can get information and files on web. for example   Verilog is listed in Known Languages section.
  2. GNU enscript from

Verilog to HTML converter

There are two converters available now. 
1. Costas Calamvokis developed Verilog to HTML converter with lots of features. His v2html perl script is a new (free!) way of viewing your verilog designs. It converts your verilog files into html with all of the keywords, comments and strings prettily colored so they stand out. More usefully, it links various design elements so that you can click on the name and see what it is. Once you have run v2html on your design you can view the files directly in your browser, or you can put them on a web server for other people to see. 

Visit and download his scripts from

2. Venkateswarlu Talapaneni of Comit Systems Inc has designed Verilog to HTML converter. 
He says ... 

Design documents are extensively getting published on web. There are not emacs mode type script facilities available to format verilog files for web publishing. I made first attempt to solve this problem. You can use this perl script to convert your verilog file to html.

In this implementation

    Comments are given green color
    keyword are made bold.
Please send your experiences , comments to me ( to make this utility more useful.


vlog2html <vlog_file> [<html_file>] 

vlog_file     Name of the Verilog file that is to be converted
html_file     Name of the output HTML file. Default is the name of the 
                                     vlog_file, with .v substituted by .html

vgrind def file 
It is available in the verilog archives as: verilog-vgrind-def.Z
Verilog / ASIC / EDA related magazines. 

Here are links to some of the available magazines. 
Integrated System Design (discontinued) Archives Available here.
Chip Design Magazine
EDN Magazine
EE Times
Cadence Plugged In Magazine

Related Web sites?

Here are some links to Verilog related sites: 

Cadmazing's DA-Related Information on the Web

Electronic Design Automation Companies

IVC (International Verilog Conference) and VHDL International Users Forum(VIUF)

DAC (Design Automation Conference)

Programmable Logic Jump Station

Veripool : Public Domain Verilog Resources

Conferences and Paper contests

Design, Verification Conference and Exhibition
Date: February 22-24, 2006
Venue: Doubletree Hotel, San Jose, CA, USA
More Information :

40th Design Automation Conference
Date : July 24-26, 2006
Venue : Moscone Center, San Francisco, CA, USA 
More Information:

The International Conference on Computer Aided Design, ICCAD-99
Date: November 06-10, 2005
Venue: DoubleTree Hotel, San Jose, CA
More Information:

ACM International Symposium on Physical Design
Date: April 9-12, 2006
Venue: San Jose, CA
More Information:

Synopsys User Group
 More Information:
This site also has synthesis, project management, low power design etc. related SNUG papers.
Note: You need to have solve-it id from Synopsys to access them.

To see other EDA related conferences visit EE Times Calendar of Trade shows and Conferences.

Books and Reference material on Verilog 
Verilog HDL : A Guide to Digital Design and Synthesis Verilog HDL : A Guide to Digital Design and Synthesis

by Samir Palnitkar 
Bk&Cd-Rom Edition Hardcover, 396 pages 
Price : $65.00 
Published by Prentice Hall 
Publication date: March 1996 
Dimensions (in inches): 9.48 x 7.13 x .98 
ISBN: 0134516753 (More information

A Practical guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog HDL Chip Design : A Practical guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog

by Douglas J. Smith
price : $65.00 
Publication date: June 1st 1996 
Large format (8.5 x 11) inches hardcover 464 pages 
ISBN: 0-9651934-3-8

Real Chip Design and Verification Using Verilog and VHDL 

by Ben Cohen
Price: $80
ISBN 0-9705394-2-8 
VhdlCohen Publishing, November 2001, 420 pages. 
(More Information)

Verilog HDL Synthesis, A Practical Primer Verilog HDL Synthesis, A Practical Primer

by J. Bhasker
236 pages; soft cover; US$49.95 (Quantity discounts)
ISBN 0-9650391-5-3
Star Galaxy Publishing (More Information)

A Verilog HDL Primer A Verilog HDL Primer

by J. Bhasker 
Price : US$59.95 (Quantity discounts) 
Published by Star Galaxy Press. (More information
ISBN: 0-9656277-4-8

Verilog Quickstart, 3rd Edition

by James M. Lee
Hardcover Published by Kluwer Academic Publishers
ISBN: 0-7923-7672-2
(More Information
Price: $98.00

Verilog Designer's Library Verilog Designer's Library

by Bob Zeidman 
Prentice Hall; ISBN: 0130811548
Hardcover - 416 pages Bk&Cd Rom edition (July
Price: $75.00
(More Information)


The Verilog Hardware Description Language The Verilog Hardware Description Language
by Thomas, D . E . / Moorby, Philip R .
Fourth Edition 
Published by Kluwer Academic Publishers
Date Published: 05/1998
ISBN: 0792381661
Price: $98.00
Hardcover; 354 Pages
Digital Design With Verilog HDL (Design Automation Series)

by Eliezer Sternheim, Rajvir Singh, Yatin Trivedi 
Paperback Price: $69.50 
Published by Chapman & Hall 
Publication date: May 1991 
ISBN: 0962748803 

"Modeling, Synthesis and Rapid Prototyping with the Verilog HDL"
 by Michael D. Ciletti.
Prentice Hall; ISBN: 0139773983  Price: $100.00
Hardcover - 727 pages Bk&Cd Rom edition (August 1999) 

IEEE Std 1364-1995 : IEEE Standard Hardware Description Language based on the Verilog Hardware Description Language
Published by the IEEE, Inc., 345 East 47th Street, New York, NY 10017, USA 
ISBN 1-55937-727-5 (More Info)

Successful ASIC Design the First Time Through
by John P. Huber, Mark W. Rosneck 
Hardcover Price: $49.95 
Published by Van Nostrand Reinhold (Short Disc) 
Publication date: May 1991 
ISBN: 0442003129 

OVI is the organization charged with Verilog standardization and language enhancements. 
For the following publications contact Lynn Horobin at the OVI office. 

Open Verilog International
Lynn Horobin 
15466 Los Gatos Blvd., Suite 109-071 
Los Gatos, CA 95032 
Phone: (408) 353-8899 -- FAX: (408) 353-8869 

  - $100 per copy, plus local sales tax 

  - $150 per copy, plus local sales tax 

  - $100 per copy, plus local sales tax


Books on HDL Verification 
"Writing testbenches: Functional Verification of
HDL Models"
by Janick Bergeron

Cover price: $US98.
ISBN 0-7923-7766-4 
(More Information)

Principles of Verifiable RTL Design "Principles of Verifiable RTL Design"
by Lionel Bening and Harry Foster

Cover price: $US98.
ISBN 0-7923-7788-5
(More Information)

Free Stuff :

Free Verilog simulator 

There are three free Verilog simulators available with limited capabilities:

Online Simulator  
Icarus Verilog: It is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2000. The standard proper is due to be release towards the middle of the year 2000. This is a fairly large and complex standard, so it will take some time for it to get there. More information and downloads are available at
The main compiler is written  by Stephen Williams 

Precompiled Windows binaries are at

ASICDesign Info page has first of its kind online simulator. It has a limitation of 30sec run time
per job. Its primary purpose is for some one interested in verilog to learn by using it without installing and learning about the tool.

SILOS III from Simucad
SILOS III's high performance logic and fault simulation environment supports the Verilog Hardware Description Language for simulation at multiple levels of abstraction. The Environment's state-of-the-art architecture incorporates an exclusive integrated /  interactive multi-tasking graphical debugging environment that provides unsurpassed accuracy and outstanding performance. 

GPL CVer from Pragmatic-C  
GPL Cver is a Verilog HDL simulator that is released under the GNU General Public License. GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM).

VeriLogger from SynaptiCAD
VeriLogger is a free an IEEE-1364 compliant Verilog simulator. VeriLogger combines many of the best ideas from modern programming IDEs and SynaptiCAD's timing diagram editing environment to created an interactive simulator with graphical stimulus generation. VeriLogger has a powerful hierarchical browser that displays the structural relationships of the modules. It also includes waveform viewing, single step debugging, point-and-click breakpoints, graphical and console execution (command line version). Download a free evaluation version of VeriLogger Pro from

SMASH from Dolphin Integration
Dolphin Integration offers evaluation version of SMASH simulator which is a mixed signal,multi-level simulator.SMASH implements the full Verilog-HDL IEEE standard. The implementation is based on the OVI Reference Manuals.
SMASH supports the SDF (Standard Delay File) format, to allow back annotation from layout tools.
This evaluation version is a full featured system (they will not allow you to compile new behavioral models though). They will not handle large circuits. The number of analog nodes is limited to 25, and the number of digital nodes is limited to 50.

VBS: VBS stands for Verilog Behavioral Simulator. Jimen Ching wrote this for his senior design project at the University of Hawaii. Since then, he has extensively added more features.

Old Verwell simulator for Linux is available at

Free Simulation Waveform Viewer

There are 4 free Verilog waveform viewers: 

Icarus Verilog Interactive (IVI for short) is an interactive front-end to the superb verilog compiler/simulator written by Stephen Williams (found at

Icarus also works with a waveform viewer, such as GTKwave
There are prepackaged RPMS for Linux here:

Precompiled Windows Version:

VeriLogger Pro from SynaptiCAD will handle small Verilog files without a license. You can download it from

Dinotrace is a X-11 waveform viewer which understands Verilog Value Change Dumps, ASCII, and other trace formats. It allows placing cursors, highlighting signals, searching, printing, and other capabilities superior to many commercial waveform viewers. 
Dinotrace is made available by  Wilson Snyder

Free Verilog Design Rule Checker

Design Rule checkers / linting tools are used for 

  • Finding out non-synthesizable constructs and potential mismatches in RTL and netlist simulations.
  • Reviewing Verilog code for company-wide reuse / consistency in style.
  • Making sure that code matches with established standards of reuse, for example Reuse Methodology manual from Synopsys/Mentor Graphics.
TransEDA offers an online demo of their HDL checker called VN-Check.
This service is free. Registration required. 
Free Timing Analyzer

The TimingAnalyzer can be used to draw and edit timing diagrams and check for timing problems in digital systems. The diagrams can be included in word processing documents, printed, and saved as JPG or GIF image files. The signal diagrams are saved as text files so they are easy to modify or distribute.

Visit Dan Fabrizio's site to learn more and download. Currently, the program is in a beta testing. While it is in beta testing anyone can use the program for free.

Free VHDL to Verilog Translator

A VHDL to Verilog RTL translator is avaliable under GPL.

The tool supports a limited but useful subset of VHDL and it has been tested on company's  JPEG and triple DES cores.

Free Verilog to C++ / System C Translator

Verilator from Veripool is a Verilog to C translator. Verilator is a Experimental program. It converts Synthesizable Verilog (not test-bench code!) into C++ or SystemC code.

Free Verilog Code Coverage Tool

Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test.

Free Verilog LRM 

An experimental Verilog LRM is available from

This material is an experimental project to link ASICs... the book with the IEEE Verilog(TM) HDL Language Reference Manual. The Verilog(TM) HDL LRM is copyright material. This project is not intended for public distribution.

Free Verilog quick reference card 
  1. On-line Verilog HDL Quick Reference Guide by Stuart Sutherland.
  3. A postscript quick reference card has been donated by Rajeev Madhavan.
  4. ref.pdf

  5. Comit Systems, Inc has published Verilog Quick Reference Card in ISD magazine September 1997. It is available free of charge. Email your postal address to  
    For engineers using Verilog & VHDL to design ASICs, HDL Quick Reference manuals have just been released for both languages on Pocket-PC, Win-CE and Palm-OS by Comit Systems, Inc. of  Santa Clara, CA.

    The Quick PDA References are available for FREE download on the
    company's website at
  6. Verilog Quick Reference card from Qualis Design  

Free Verilog Tutorials

There are two quality interactive tutorials available on web currently.

    Doulos HDL Associates offers Verilog HDL - Entry Edition free. It is Computer Based Multimedia Interactive Training. It is not a demonstrator but a practical introduction to Verilog and synthesis to get you up and running with Verilog.
    It is currently available absolutely free from Doulos and can be downloaded directly from the web.

    ALDEC, Inc.
    EVITA Verilog is available at at no cost. It includes a complete Verilog reference guide with design samples and interactive Verilog tutorial. EVITA Verilog is aimed at hardware designers who have little or no Verilog experience and want to start getting involved with HDL based designs.

Other three online tutorials
Prof. Don Thomas, carnegie Mellon University.
The Verilog Hardware Description Language
Dr. Daniel C. Hyde's Handbook on Verilog HDL. 
A short but in-depth introduction to Verilog HDL.
A pdf version for easy printing is available here.

Gerard M Blair's Online Verilog manual at University of Edinburgh is also very useful introduction.

Free Verilog Obfuscator 

Sometimes you want to ship your Verilog code without giving away your intellectual property. The simplest way to do is obfuscate it. You can find such obfuscater at

Public domain Verilog preprocessor 

Himanshu M. Thaker has written a Verilog Preprocessor which supports "generate" like statements known from VHDL. It is available from SureFire Verification Inc site.


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Copyright Rajesh Bawankule  1997 - 2005