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Productivity Tools

Front End Tools

RTL code generators / IP Cores

Verification and Simulation Control Tools

Synthesis Related Tools

Emacs Modes
Verilog : Michael McNamara maintains Verilog Mode for Emacs. You can download it from its own web page 

Vera : Reto Zimmermann maintains Emacs mode for Vera. Vera is a hardware verification language (HVL) from Synopsys. It is available at  or from author's page.

Dcsh (dc_shell) : A simple Emacs Dcsh Mode for scripting language of Synopsys' Design Compiler is available at  or from author's page.
   The mode includes the following features:
   - Syntax highlighting 
   - Indentation 
   - Word/keyword completion 
   - Block commenting 
   - Works under GNU Emacs and XEmacs 

vim modes 
vim is, vi improved. It is a vi-like editor with color syntax highlighting.  More information about vim is available at:

Verilog : Jeff Solomon maintains his page on vim syntax files for Verilog along with C, perl, csh, Tcl at

Vera: Beth Leonard of Hewlett-Packard posted this vim syntax file for vera in ESNUG.

Design Compiler: Gzim Derti posted this vim syntax file file for synthesis in ESNUG.

Timing Diagram Tool

TimingTool is a free to use on-line Timing Diagram Editor.  This tool provides very good VHDL and Verilog test benches and requires no download or installation.

A more advanced application version of this tool including an HDL editor is available from Saros and is called TurboWriterPro.  This can be downloaded for evaluation from:

Revision Control Software
CVS is widely used revision control software. The Concurrent Versions System (CVS) provides network-transparent source control for groups of developers. 

  • maintains a history of all changes made to each directory tree it manages 
  • provides hooks to support process control and change control 
  • provides reliable access to its directory trees from remote hosts using Internet protocols 
  • supports parallel development allowing more than one developer to work on the same sources at the same time 
One can download CVS binaries and source at
An excellent documentation is available at

Synthesizable Arithmetic Module Generator
Generate synthesizable adders, subtractor, multiplier, squarer with this fully configurable web based tool.

It is developed by Johnny Pihl - Espen Sand of Norwegian University of Science and Technology. More information of this project is available at

Synthesizable CRC functions
Generate synthesizable CRC functions with web based tool from Easics

More theoretical information on crc is available at

vpp: A Powerful Verilog Preprocessor
Hemi Thaker wrote this utility to emulate VHDL's "generate" statement.
For example the code fragment shown on left side will get converted into code fragment shown on right side after passing through vpp Verilog preprocessor.
It is available at
`for (i=0; i<4; i++)
`let j=i*2;
    addr addr::`i (
        .a (a[`j])
addr addr0 (
        .a (a[0])
    addr addr1 (
        .a (a[2])
    addr addr2 (
        .a (a[4])
    addr addr3 (
        .a (a[6])

OpenCores ( )
This site is created to to coordinates efforts of creating open source IP cores. Lots of good cores are available on this site including microprocessor, arithmetic, communication cores.

Jeda (Juniper EDA ? :) ( )
Atsushi Kasuya of Juniper Networks Inc. developed Jeda. It is a C-like programming language for hardware design verification. It has Verilog-like multi-value bit vector data type and concurrent programming features with the garbage collection support. It also provides object oriented programming support.

Jeda links to Verilog as a user PLI code and runs with Verilog. 

The Open Verification Library (OVL) 
Harry Foster who wrote "Principles of Verifiable RTL Design" started this OVL website to spread the use of assertion monitor. These initial assertion monitors specifications are donated by Verplex to OVL. 

OpenVera ( )
OpenVera 2.0 combines the strengths of the OpenVera hardware verification language from Synopsys with Intel’s newest formal verification language (ForSpec) to deliver a more comprehensive, open source hardware verification language to the verification community.

Testbuilder ( )
TestBuilder provides a C++ signal class, interfacing C++ to an HDL design at the signal level. TestBuilder supports abstraction of tests to the transaction level. It provides concurrency (threading), including dynamic generation of and synchronization between concurrent tasks. TestBuilder supports both Verilog and VHDL.

Cadence developed Testbuilder but could not make a dent in market as they were late in the game. Making it free / open source may entice many engineers to try and build a user base.

logscan :  A Configurable Error Management Utility
David C. Black, Qualis Design wrote this perl script to extract exact "information" from huge reports generated by tools like Synopsys Design Compiler etc. This fully configurable script extracts information you need from thousands of errors and warning messages the tools generate. It is available at

ScriptSim : Bring the power of Perl/Tk and Python/Tk to your Verilog® simulations
ScriptSim integrates perl and python including Tk with your verilog simulation. ScriptSim interfaces to any Verilog PLI compliant simulator and dynamically creates perl and/or python processes running your model or verification scripts. With the Perl/Tk or Python/Tk interfaces, your scripts can create professional user interfaces with multiple windows, graphics, and mouse interaction, or you can use the built-in Tk display created automatically by ScriptSim.

Perl-interface to speed up verification times with SimWave by Utku Ozcan.
This program generates compact $shm_probe task as a Verilog output which can be included in this testbench file. Detailed description and perl code is available here.

Code Coverage Tool

Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. A preliminary version is available at

Synopsys Plus Perl (SPP)
SPP is a Perl module that wraps around Synopsys' shell programs developed by Jeff Solomon. SPP is inspired by the original dc_perl written by Steve Golson, but it's an entirely new implementation. Why is it called SPP and not dc_perl? Well, SPP was written to wrap around any of Synopsys' shells.  This includes:


However, that's not really the whole story. SPP is a Perl module, not an application. It can be used to fully embed a Synopsys script inside of Perl.  SPP was written in an object-oriented way so that each object totally encloses a Synopsys shell process.

The first example of an application using SPP is called synopsys_fe, a frontend replacement for any of the Synopsys shells listed above. synopsys_fe sports a snazzy GNU Readline interface with all of your favorite terminal capabilities (command completion, up/down history, etc), a convenient Perl interface, and other Perl niceties that you might expect.

But wait, there's more! Invoking the Synopsys shell in Tcl mode (SPP supports both Tcl and default Dcsh mode), enables an auxiliary module, Synopsys::Collection. This module maps the functionality provided by Synopsys' collection idiom into Perl.

Sound interesting? Click on
SPP is free software. Anyone can redistribute it and/or modify it under the same terms as Perl itself. Feel free to contact Jeff ( with any questions, comments, criticisms you have.

IPOfix - A Freeware IPO Buffer Resizing Program
Jeff Winston of Maker Communications wrote this C program to read in Synopsys Primetime ® timing reports and upsizes gates whose individual delays exceed user-specified limits. A detailed information is available at and source code is available for download here.

ScriptEDA: Link scripting languages such as Perl and Tcl to any freely available EDA tools
This page is dedicated to linking scripting languages such as Perl,Python and Tcl to any freely available EDA tools. Basic idea is to make friendly interfaces for any existing EDA engines


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