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Perl interface to speed up verification times with SimWave

by Utku Ozcan

$shm_probe Generator, ver 3.0.

Utku Ozcan, ASIC/FPGA Designer, Netas, Turkey.
E-mail Address:

Update Note: This interface has been redesigned in Perl, in order to free designer from compiling things. It can be run immediately.

This Perl-interface generates Verilog file from, which is configuration file of SimWave, Waveform Display program of Cadence. Verilog file include $simwave PLI task that might speed up verification times.

This program has been tested with Perl 5.00503, and tested on Verilog-XL Simulator 2.6.36 and SimWave. Environment: Sun Solaris 2.6 and test chip is made up of 300kgates.

Normally, when you want to add signals to SHM databases to see the signals of the chip in waveforms, you might use following command:

$shm_probe (test_bench, "AC");

But if the chip is big and if the simulation time is long, this simple command might create a simulation database of gigabytes, which might cause a file system error (beyond the UNIX limit of file size).

The only way to make the simulation database smaller is to write down each necessary signal into the $shm_probe signal individually. But this is also a tiring job.

I have found a simpler way to generate this compact $shm_probe task.
Do the following:

1. Use $shm_probe (test_bench, "AC"); first.
2. Run the simulation for a very short time, such 10 ns.
3. Open SimWave and choose your signals.
4. Save Setup file. This will create your own .sv file.
5. Run Perl code and pass the name of the SimWaev setup file as command line argument to the executable and Verilog output filename as the second command line argument: -s <input_file> -d <output_file>

6. Program will generate shm_probe_gen.v file, which includes
$shm_open ("<your_database>.shm"); and $shm_open (<your_signals>);
7. Then go to your testbench and remove your $shm_open and $shm_probe
tasks, instead, `include output filename.

Selecting signals in the SimWave, rather than writing down those into $shm_probe task, is relatively quite easy. This technique has been tested on a 300k gate chip. Its postlayout simulation lasted 36 hours of CPU time (50 ms.) and SHM database was the size of 2.2 Gigabytes and the program crashed due to file system error. After having used the Perl-interface, SHM Database has been the size of 20 Megabytes (100 time smaller) and CPU time of the simulation has been 30 hours.

Following limitations are addressed here:

1. Program cannot resolve signal names from aliases (bus names).
2. Program cannot resolve signal names from Groups.
3. Input file must be real .sv file, other files may corrupt (corrected in v3.0)


Utku Ozcan

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