Post Codes

POST Codes are hexadecimal codes generated by the BIOS during the POST operation.  These codes may be monitored on a special hardware "Post card" which displays them using a two digit alphanumeric display.  

·         ISA Post codes are output to port address 80h.

·         EISA Post codes are typically output to port address 300h.

Code (hex)

Name

Description

co

Turn off Chipset Cache

OEM Specific-Cache control

1

Processor Test 1

Processor status (1FLAGS) Verification.Tests the following processor status flags: carry, zero, sign, overflow.

The BIOS sets each flag, verifies they are set, then turns each flag off and verifies it is off.

2

Processor Test 2

Read/Write/Verify all CPU registers except SS, SP, and BP with data pattern FF and 00.

3

Initialize Chips

Disable NMI, PIE, AIE, UEI, SQWV.

Disable video, parity checking, DMA.

Reset math coprocessor.

Clear all page registers, CMOS shutdown byte.

Initialize timer 0,1, and 2, including set EISA timer to a known state.

Initialize DMA controllers 0 and 1.

Initialize interrupt controllers 0 and 1.

Initialize EISA extended registers.

4

Test Memory Refresh Toggle

RAM must be periodically refreshed to keep the memory from decaying. This refresh function is working properly.

5

Blank video, Initialize keyboard

Keyboard controller initialization.

6

Reserved

7

Test CMOS Interface and Battery Status

Verifies CMOS is working correctly, detects bad battery.

BE

Chipset Default Initialization

Program Chipset registers with power on BIOS defaults

CI

Memory presence test

OEM Specific-Test to size on-board memory.

C5

Early Shadow

OEM Specific-Early Shadow enable for fast boot.

C6

Cache presence test

External cache size detection.

8

Setup low memory

Early chip set initialization.

Memory presence test.

OEM chip set routines.

Clear low 64K of memory.

Test first 64K memory.

9

Early Cache Initialization

Cyrix CPU initialization.

Cache initialization.

A

Setup Interrupt Vector Table

Initialize first 120 interrupt vectors with SPURIOUS_INT_HDLR and initialize INT 00h-1Fh according to INT_TBL.

B

Test CMOS RAM Checksum

Test CMOS RAM checksum, if bad, or insert key pressed, load defaults.

C

Initialize Video Interface

Detect type of keyboard controller (optional).

Set NUM_LOCK status.

D

Initialize Video Interface

Detect CPU clock.

Read CMOS location 14h to find out type of video in use.

Detect and Initialize Video Adapter.

E

Test Video Memory

Test video memory, write sign-on message to screen.

Setup shadow RAM ö Enable shadow according to Setup.

F

Test DMA

BIOS checksum test.

Controller 0

Keyboard detect and initialization.

10

Test DMA Controller 1

Test DMA Controller 1.

11

Test DMA Page Registers

Test DMA Page Registers.

12-13

Reserved

14

Test Timer Counter 2

Test 8254 Timer 0 Counter 2.

15

Test 8259-1 Mask Bits

Verify 8259 Channel 1 masked interrupts by alternately turning off and on the interrupt lines.

16

Test 8259-2 Mask Bits

Verify 8259 Channel 2 masked interrupts by alternately turning off and on the interrupt lines

17

Test Stuck 8259âs Interrupt Bits

Turn off interrupts then verify no interrupt mask register is on.

18

Test 8259 Interrupt Functionality

Force an interrupt and verify the interrupt occurred.

19

Test Stuck NMI

Verify NMI can be cleared.

1A

Display CPU clock.

1B-1E

Reserved

1F

Set EISA Mode

If EISA non-volatile memory checksum is good, execute EISA initialization.

If not, execute ISA tests an clear

EISA mode flag.

Test EISA Configuration Memory

Integrity (checksum & communication interface).

20

Enable Slot 0

Initialize slot 0 (System Board).

21-2F

Enable Slots 1-15

Initialize slots 1 through 15.

30

Size Base and Extended Memory

Size base memory from 256K to 640K and extended memory above 1MB.