Interesting Papers on ASIC and Digital
Insightful papers on Verilog-VHDL comparison
Papers on Metastability
University of Queensland Electrical and Computer Engineering Notes
metastability from killing your digital design
: Debora Grosse
Synchronizing asynchronous signals causes
metastability, which makes it difficult to iron out the bugs during system
test. Paying close attention to the synchronizer and some metastability
equations can help you avoid the pitfalls.
Response in 5-V Logic Circuits
This document describes metastable response
in digital circuits. After a definition of a metastable state, a test circuit
is provided, its responses analyzed, and test results given. Examples show
the influence of metastability on the response of asynchronous circuits
and measures for improving reliability are assessed.
Summary: Metastability is unavoidable in asynchronous
systems. However, using the formulas and test measurements
supplied here, designers can calculate the probability of failure.
Design techniques for minimizing metastability are also provided.
Application Note by P. Alfke and B. Philofsky. Description
of metastable states, measurement techniques, tables of metastable parameters,
and a summary graph.
Recovery in Xilinx FPGAs,"
Section Contents and Abstracts. Are Your PLDs Metastable?
note provides a detailed description of the metastable behavior.