IntroductionThis contribution came from a discussion on the comp.lang.verilog bulletin board which was initiated by Farhad Sunavala concerning RAM modelling. Thanks go to t he several people who contributed to the discussion and to Farhad, for summarizing the discussion here.
The question was, "how do you model a RAM in Verilog?" Assume the following:
Solution 1:Farhad's original version was:
This works fine since the RAM inputs & outputs are separate. However, consider t he case of a RAM where the input data and output data are one inout port:
Solution 1 does not work for this case since the bidirectional data bus cannot b e declared as a register in the module.
Solution 2:Gary Cook (BNR Europe) suggested the following:
The assign puts the stored 'data' onto the d_q bus when r_wb is high, ie indicat ing a read. When d_q is low , the assign tri-states the d_q which can be driven by the driving device.
[Ed. note: This solution has several potential gotchas. What does this model do if addr and r_wb change at the same time?]
Solution 3:David McGhee (University of Alabama) contributed the following:
Here's an example of how I do memories - tribuf8 is a module that contains 8 tri -state buffers:
[Ed. note: Check out the use of a non-blocking assign in the write to memoryspac e. Is this correct? Hint: the delay should be an intra-assignment delay. Then, t he assignment can be either blocking or non-blocking.]
ConclusionModelling a RAM is a common thing to do in Verilog, and there are a variety of ways to do it. Most all are some variation on using a bidirectional port with a conditional driver, either a conditional continuous assignment or a tri-state buffer.
Copyright Rajesh Bawankule 1997-2003