Design and VHDL Implementation of a Non-pipelined Complex Multiplier Accumulator

Many digital signal processing algorithms, including FFT, filtering/equalization, and demodulation, making use of multiplier accumulators (MAC). A complex MAC operates on two sequences of complex number {xi} and {yi}. The MAC multiplies corresponding elements of the sequences and accumulates the sum of the products. The results is

N

Sigma xiyi

i =1

Where N is the length of the sequences. Each complex number is represented in Cartesian form, consisting of a real and an imaginary part. If we are given two complex numbers x and y, their product is a complex number p, calculated as follows:

p_real = x_real x y_real - x_imag x y_imag

p_imag = x_real x y_imag + x_imag x y_real

The sum of x and y is a complex number s calculated as follows:

s_real = x_real + y_real

s_imag = x_imag + y_imag

MAC calculates its results by taking successive pairs of complex numbers, one each from the two input sequences, forming their complex product and adding it to an accumulator register. The accumulator is initially cleared to zero and is reset after each pair of sequences has been processed. An architecture for the MAC is given in the following figure:

Data is represented with a 16 bit, two's fixed -point binary representation. Each of the real and imaginary parts of the two complex numbers and the complex output of the MAC uses the same representation where bit 15 is the sign bit and the binary point is assumed to be between bits 15 and 14. This format will facilitate numbers in the range -1 (inclusive) to +1 (exclusive) with a resolution of 2*exp(-15). This raises the possibility of overflow occurring while summing a sequence of numbers, so we include an overflow status signal in the design. Overflow can occur in two cases. First, intermediate partial sums may fall outside the range -1 to +1. We can reduce the likelihood of this happening by expanding the range used to represent intermediate results to -16 to +16. However, if an intermediate sum falls outside of the expanded range, the summation for the entire sequence is in error, so the overflow signal must be set. It remains set until the accumulator is cleared, indicating the end of the summation. The second overflow case happens if the final sum falls outside the range of values representable by the MAC output. This may be a transient condition, since a subsequent product, when added to the sum, may bring the sum back in range. Assert the overflow signal only during a cycle in which the final sum is out of range, rather than latching the overflow until the end of summation.

Requirements:

Design a non-pipelined multiplier accumulator for a stream of complex numbers.

1. Develop a behavioral VHDL model for the complex MAC. Simulate you VHDL model and test its functionality with an appropriate test bench.

2. Develop a structural model in VHDL for the complex MAC. Simulate your VHDL model and test its functionality with an appropriate test bench.

The VHDL entity description for the non-piplined complex multiplier accumulator is given as follows:

Library IEEE;

port ( clk, clr: in std_logic;

x_real: in std_logic_vector (15 downto 0);

x_imag: in std_logic_vector (15 downto 0);

y_real: in std_logic_vector (15 downto 0);

y_imag: in std_logic_vector (15 downto 0);

s_real: out std_logic_vector (15 downto 0);

s_imag: out std_logic_vector (15 downto 0);

ovf: out std_logic);