Figure 8.35. There are 3 inputs on the left labeled eh, B, and C. Each input goes to the input of an inverter. The outputs of the inverters are, not eh, not B, and not C. Farther to the right there are 3 3-input NAND gates labeled 1, 2, and 3. The inputs to gate 1 are eh, not B, and not C. The inputs to gate 2 are, not eh, not B, and C. The inputs to gate 3 are, eh, B, and C. The outputs of gates 1 2 and 3 go to gate 4, which is also a 3 input NAND gate. The output of gate 4 is the output of the circuit. End verbal description.
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