Figure 8.16. Input eh goes to one of the inputs of a two input NAND gate. Input B goes to another two input NAND gate but the two inputs are tied together and input B goes to both of them. The output of this gate goes to the other input of the first gate. The output of this gate goes to a third 2 input NAND gate which also has both inputs tied together. The output of this third gate is variable D. End verbal description.
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