186
INTx/ INTAx Errata
Description

Rev.
03 8/20/92
Introduction
An internal
problem with the Interrupt Control Unit is cascade mode can
cause no acknowledge cycle on the INTA1# line after an
interrupt on INT1 or on INTA0# after an interrupt on INT0. If
two cascaded interrupt controllers are used, the interrupt
acknowledge can be sent to the wrong controller. Because the
interrupt timing is critical for the error to occur, there may
be several minutes or hours of flawless operation between
occurrences. There are two cases. Problem 1: Interrupt 1 is
configured in cascaded mode and a higher priority interrupt
exists. Problem 2: Interrupt 0 is configured in cascaded mode
and interrupt 1 is higher priority.
The devices affected may be identified by the 9 character
alphanumeric Intel FPO number underneath the product code
number. The ninth character is an identifier that relates to
the stepping as indicated in Table 1.
Device |
Stepping |
9th
Character |
80C186XL/80C188XL |
B |
A |
80C186EA/80C188EA |
A |
A |
80C186EA/80C188EA |
B |
B |
80L186EA/80L188EA |
B |
B |
80C186EB/80C188EB |
A |
A* |
80C186EB/80C188EB |
B0 |
B |
80C186EB/80C188EB |
B1 |
C |
80L186EB/80L188EB |
A |
A* |
80L186EB/80L188EB |
B0 |
B |
80L186EB/80L188EB |
B1 |
C |
Table 1. Parts affected by the INTx/INTAx errata
*NOTE: This problem does not occur on
the 80C186/80C188 or 80C186EC/80C188EC.
*NOTE:
A-Step material may be identified by no ninth character.
Errata Description
Problem 1:
An interrupt acknowledge for INT1 is not
generated on INTA1#. If two interrupts are in cascade mode,
the interrupt acknowledge is generated on INTA0#
Condition:
Another interrupt of higher priority
occurs after the decision is made to service Interrupt 1 but
before the expected acknowledge cycle on INTA1#.
Configuration:
1). Master Mode
2). INT 1 is in
Cascade mode and enabled.
3). An Interrupt of higher
priority than INT1 is enabled (DMA, Timers, INT lines, Serial,
etc.)
Problem 2:
An interrupt acknowledge for INT0 is
not generated on INTA0#. If two interrupts are in cascade
mode, the interrupt acknowledge is generated on INTA1#
Condition:
Interrupt 1, configured as higher
priority than interrupt 0, occurs after the decision is made
to service Interrupt 0 but before the expected acknowledge
cycle on INTA0#.
Configuration:
1). Master Mode
2). INT 0 is in
Cascade mode and enabled.
3). INT 1 is enabled and higher
priority than INT0.
Problem 1 Description
NOTE: In the cases below, the interrupt controller has
already decided to service the INT1 interrupt before the
higher priority interrupt occurs.
Correct operation of the device acknowledges the interrupt
on INTA1# after an interrupt on INT1. Normally, this occurs
even if there is a higher priority interrupt after INT1 but
before the acknowledge (Figure 1).
Figure
1. Correct INT 1 Acknowledge sequence with higher priority
Timer interrupt
*NOTE: This interrupt could be any of the
following: DMA, Timers, Serial, INT0, or INT2.
The errata occurs when a higher priority interrupt occurs
between INT 1 and its expected acknowledge. The processor
completes internal interrupt acknowledge cycles as seen on the
status lines but no acknowledge cycle is sent on the INTA1#
output (Figure 2).
Figure
2. Incorrect INT 1 Acknowledge sequence with a higher priority
Timer Interrupt
*NOTE: This interrupt could be any of the
following: DMA, Timers, Serial, INT0, or INT2.
If INT 0 and INT 1 are configured in cascade mode and a
higher priority interrupt occurs between INT 1 and its
expected acknowledge, then the acknowledge will appear on
INTA0# instead (Figure 3).
Figure
3. INT 0 and INT 1 Acknowledge Failure due to higher priority
Timer Interrupt
*NOTE: This interrupt could be any of the following:
DMA, Timers, Serial, or INT 0.
Problem 2
Description
*NOTE: In the cases below,
the interrupt controller has already decided to service the
INT 0 interrupt before the higher priority INT 1 occurs.
Correct operation acknowledges INT 0 on INTA0#. Normally,
this occurs even if there is a higher priority INT 1 after INT
0 but before the acknowledge (Figure 4).
Figure
4. Correct INT 0 Acknowledge operation with a simultaneous INT
1
*NOTE: INT 1 is the only interrupt that causes the
errata to occur. The errata occurs when INT 1, which is higher
priority than INT 0, occurs between INT 0 and its expected
acknowledge. The processor completes internal interrupt
acknowledge cycles as seen on the status lines but no
acknowledge cycle is sent on the INTA0# output (Figure 5).
Figure
5. Incorrect INT 0 Acknowledge operation with a simultaneous
INT 1
*NOTE: This problem occurs only if INT 1 is
higher priority than INT 0.
If INT 0 and INT 1 are configured in cascade mode and the
higher priority INT 1 occurs between INT 0 and its expected
acknowledge, then the acknowledge will appear on INTA1#
instead of INTA0# (Figure 6).
Figure
6. INT 0 and INT 1 Acknowledge Failure due to the higher
priority INT 1.
*NOTE: This problem occurs only if INT 1 is
higher priority than INT 0.
Software Workarounds
Tables 2
and 3 provide possible solutions to different system interrupt
configurations that can occur.
|
Condition |
Workaround |
1) |
Only INT 1 is configured in
cascade mode and is lower priority than at least one
other interrupt. |
Use only INT 0 in cascade
mode instead, or make INT 1 the highest priority
interrupt, or implement hardware
workaround. |
2) |
INT 1 and INT 0 are both in
cascade mode. |
Use only one interrupt in
cascade mode, or implement hardware
workaround. |
3) |
Only INT 0 is configured in
cascade mode and is lower priortiy than INT 1. |
Make INT 0 higher priority
than INT 1, or implement hardware
workaround. |
Master Mode |
Cascade Mode |
INT 1 Priority vs any
other interrupt |
INTA1 Problem |
INTA0 Problem |
Workaround |
Yes |
INT0 and INT1 |
N/A |
Yes |
Yes |
Use only one interrupt line
in cascade mode or H/W workaround |
Yes |
INT1 only |
Lower |
Yes |
No |
Change to INT0 or make INT1
highest priority |
Yes |
INT1 only |
Higher |
No |
No |
N/A |
Yes |
INT0 only |
N/A |
No |
Yes |
See Table 3 |
No |
N/A |
N/A |
No |
No |
N/A |
Table 2. Software workarounds for problem 1.
Master Mode |
Cascade Mode |
INT 0 Priority vs any INT
1 |
INTA0 Problem |
INTA1 Problem |
Work
around |
Yes |
INT0 and INT1 |
N/A |
Yes |
Yes |
Use only one interrupt line
in cascade mode or H/W workaround |
Yes |
INT0 only |
Lower |
Yes |
No |
Make INT0 highest
priority |
Yes |
INT0 only |
Higher |
No |
No |
N/A |
Yes |
INT1 only |
N/A |
No |
Yes |
See Table 2 |
No |
N/A |
N/A |
No |
No |
N/A |
Table 3. Software workarounds for problem 2.
Hardware Workaround
The
hardware workarounds for systems with a single cascaded
interrupt and two cascaded interrupts are identical. The
workarounds only differ in the software considerations. The
simple case of a single cascaded interrupt will be shown with
details on how to alter this solution to account for two
cascaded interrupts.
Single Cascaded Interrupt
In a system with a single external interrupt controller,
the errata will cause no acknowledge to be sent on the INTA#
output. Internally, the device still functions normally, only
the state of the output pin is incorrect. The Interrupt
Request Register and Interrupt Service Register will operate
normally.
The 186 will still run two back-to back interrupt
acknowledge cycles. If the external interrupt controller does
not receive the two interrupt acknowledge pulses, it will
never drive the interrupt type onto the data bus. Therefore,
the 186 will read an invalid interrupt type.
The hardware part of the solution is to pull up the lower 8
bits of the data bus to Vcc through pull-up resistors. These
resistors will pull the floated bus to 0FFH during the 186
interrupt acknowledge cycle. A type 255 interrupt will be read
from the bus and executed. An interrupt service routine for a
type 255 interrupt should be included in the software. This
solution allows a graceful recovery from the errata condition.
If the current design uses interrupt type 255, the resistors
can be selectively connected to Vcc or Ground to define an
unused interrupt type.
Now that the system has recovered from the errata, the
original interrupts must be serviced. The higher priority
interrupt will execute next. Finally the interrupt request
from the external interrupt controller must be serviced. This
requires that the interrupt input to the 186 be
level-sensitive, otherwise, the 186 will not recognize that
the interrupt is still active. If the interrupt input is
level-sensitive, the cascaded interrupt will then be serviced.
Dual Cascaded Interrupts
The errata differs slightly in systems with two
external interrupt controllers. When the errata occurs because
of a higher priority internal interrupt, the wrong INTA#
signal will become active. If an 8259 receives an acknowledge
and no interrupt is present, it assumes a spurious interrupt
occurred and issues an interrupt 7. The service routine for
this interrupt must be included in the software.
The situation where the interaction between INT 0 and INT 1
causes the errata is a special case. This situation will occur
as just described, the INTA# pulse will be issued to the wrong
8259. In this situation, the interrupt input to the wrong 8259
is active when the acknowledge occurs. This is not
really a problem. The acknowledged 8259 will drive its
interrupt type onto the bus, and the CPU will service that
interrupt. The only difficulty is what happens internally to
the 186. The incorrect Interrupt Request and Service Bits have
been set. To recover from this, the interrupt service routine
must issue a non-specific End of Interrupt command. At this
point, the wrong interrupt has been serviced correctly and
because the interrupt inputs are configured to be level
sensitive, the initial interrupt is now serviced.
Hardware Workaround Summary
To have a complete hardware workaround for the
INTx/INTAx errata, the following must be done:
1) Pull data bus lines 0 to 7 to a known value to force a
define value on the bus when the errata occurs.
2) Program cascaded interrupt inputs on the 186 to be level
sensitive.
3) Write a simple service routine for the interrupt type
defined in step 1.
4) Write a simple service routine for an 8259 interrupt 7
(only for cases with two external interrupt controllers).
5) Issue non-specific End of Interrupt commands in INT 0
and INT 1 service routines (only for cases with two external
interrupt controllers).