The processor returns this exception when it encounters a divide
fault. A divide fault occurs if division by zero is attempted or if the result
of the operation does not fit in the destination operand.
Interrupt 2 is reserved for the hardware Non-Maskable-Interrupt
condition. No exceptions trap through interrupt 2.
The overflow trap occurs after an INTO instruction has executed
and the 0F bit is set to 1.
The BOUND instruction compares the array index with an upper and
lower bound. If the index is out of range, then the processor traps to
interrupt 05.
This error is returned if any one of the following conditions
exists:
This error occurs if the computer does not have a math coprocessor
and the EM bit of register CR0 is set indicating that Numeric Data Processor
emulation is being used. Each time a floating point operation is executed, an
interrupt 07 occurs.
This error also occurs when a math coprocessor is used and a task switch is
executed. Interrupt 07 tells the processor that the current state of the
coprocessor needs to be saved so that it can be used by another task.
Processing an exception sometimes triggers a second exception. In
the event that this occurs, the processor will issue a interrupt 08 for a
double fault.
This error occurs when a floating point instruction causes a
memory access that runs beyond the end of the segment. If the starting address
of the floating point operand is outside the segment, then a General Protection
Fault occurs (interrupt 0D).
Because the Task State Segment contains a number of descriptors,
any number of conditions can cause exception 0A. Typically, the processor can
gather enough information from the Task State Segment to issue another fault
pointing to the actual problem. See Microsoft's Programming the 80386/80486
Guide for more information.
The Not present interrupt allows the operating system to implement
virtual memory through the segmentation mechanism. When a segment is marked as
"not present," the segment is swapped out to disk. The interrupt 0B
fault is triggered when an application needs access to the segment.
A Stack Fault occurs with error code 0 if an instruction refers to
memory beyond the limit of the stack segment. If the operating system supports
expand-down segments, increasing the size of the stack should alleviate the
problem. Loading the Stack Segment with invalid descriptors will result in a
general protection fault.
Any condition that is not covered by any of the other processor
exceptions will result in a general protection fault. The exception indicates
that this program has been corrupted in memory, usually resulting in immediate
termination of the program.
The Page Fault interrupt allows the operating system to implement
virtual memory on a demand-paged basis. An interrupt 14 usually is issued when
an access to a page directory entry or page table with the present bit set to 0
(Not present) occurs. The operating system makes the page present (usually
retrieves the page from virtual memory) and re-issues the faulting instruction,
which then can access the segment. A page fault also occurs when a paging
protection rule is violated (when the retrieve fails, or data retrieved is
invalid, or the code that issued the fault broke the protection rule for the
processor). In these cases the operating system takes over for the appropriate
action.
This interrupt occurs when an unmasked floating-point exception
has signaled a previous instruction. (Because the 80386 does not have access to
the Floating Point unit, it checks the ERROR\ pin to test for this condition.)
This is also triggered by a WAIT instruction if the Emulate Math Coprocessor
bit at CR0 is set.
This interrupt is only used on the 80486 CPUs. An interrupt 17 is
issued when code executing at ring privilege 3 attempts to access a word
operand that is not on an even-address boundary, a double-word operand that is
not divisible by four, or a long real or temp real whose address is not
divisible by eight. Alignment checking is disabled when the CPU is first
powered up and is only enabled in protected mode.
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