OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 7.1.0.253 SF [Beta #010]B(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved.; RCircuitOx?@ MS Sans Serif >74190: Synchronous up/down counter with down/up mode controlSymbol????@3333??C((T_05FF261C20080901100812CT_05FF283020080901100812CT_05FF2A2820080901100812CT_05FF2C2020080901100812? P PT_05FF2E1820080901100812;HHHHT_05FF301020080901100812?PHPHHT_05FF320820080901100812;HHHHT_05FF340020080901100812;HPHPT_05FF35F820080901100812CHp HHpp T_05FF37F020080901100812;HHHHT_05FF39E820080901100812;HHHHT_05FF3BE020080901100812;    T_05FF3DD820080901100812GP P88  T_05FEF39C20080901100812;HPHPT_05FED23420080901100812;HPHPT_05FF0ED820080901100812;HPHPT_05FED7D020080901100812;HPHPT_05FF112C20080901100812;XXT_05FEE71820080901100812;XXT_05FEF54420080901100812;XXT_05FEF6EC20080901100812;(X(XT_05FEF89420080901100812GT_05FEFA3C20080901100812GT_05FEFBE420080901100812GT_05FEFD8C20080901100812G   T_05FEFF3420080901100812G(((T_05FF00DC20080901100812G000T_05FE499420080901100812G888T_05FE4B3C20080901100812?(h x(h h xT_0E0169F8200809011009229 LOADT_02D7C2AC20041028234611ư>?Mb@?ǺF?@9p LT_02D7C5D020041028234611ư>?@9 CLKT_02D7C8BC20041028234611@@?MbP?חA:0yE>@9e  CLKT_02D7540C2004102823461129XpU2T_0023719420041029135948DIP16 (74190)SN74190TTL9f LOADT_0028582420041029140036:9 U1 T_0780E724200411040114461xx makro2.vhdSCK#xLabel+C @0H d*a ( @d*b ( @d*c ( @d*d ( @d*e ( @d*fH ( @d*g (0 @d*i0 @d*i1 @d*i2 @d*i3 @f @g"DecoderArial/۶m۶m?U@U@_%------------------------------------%-- TINA VHDL Macro Description Begin---- entity_name: BCD;-- arch_name: Behavioral;%-- ports: i0,i1,i2,i3;a,b,c,d,e,f,g;--#-- TINA VHDL Macro Description End%------------------------------------LIBRARY ieee;USE ieee.std_logic_1164.all;Package BCD_Pack is  COMPONENT BCD_Vec IS PORT (& I: IN STD_LOGIC_VECTOR(3 DOWNTO 0);, Segs: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END COMPONENT; End BCD_Pack;LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY BCD_Vec IS PORT (% I: IN STD_LOGIC_VECTOR(3 DOWNTO 0);+ Segs: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ); END BCD_Vec;.ARCHITECTURE Behavioral_BCD_Vec OF BCD_Vec ISBEGIN PROCESS( I ) BEGIN CASE I IS* WHEN "0000" => Segs <= "0000001"; -- 0* WHEN "0001" => Segs <= "1001111"; -- 1* WHEN "0010" => Segs <= "0010010"; -- 2* WHEN "0011" => Segs <= "0000110"; -- 3* WHEN "0100" => Segs <= "1001100"; -- 4* WHEN "0101" => Segs <= "0100100"; -- 5* WHEN "0110" => Segs <= "0100000"; -- 6* WHEN "0111" => Segs <= "0001111"; -- 7* WHEN "1000" => Segs <= "0000000"; -- 8* WHEN "1001" => Segs <= "0001100"; -- 9* WHEN "1010" => Segs <= "0001000"; -- A* WHEN "1011" => Segs <= "1100000"; -- b* WHEN "1100" => Segs <= "0110001"; -- C* WHEN "1101" => Segs <= "1000010"; -- d* WHEN "1110" => Segs <= "0110000"; -- E* WHEN "1111" => Segs <= "0111000"; -- F0 WHEN OTHERS => Segs <= "1111111"; -- all off END CASE;  END PROCESS;END Behavioral_BCD_Vec;LIBRARY ieee;USE ieee.std_logic_1164.all;USE work.BCD_Pack.all;ENTITY BCD IS PORT ( i3, i2, i1, i0: IN STD_LOGIC;' a, b, c, d, e, f, g: OUT STD_LOGIC ); END BCD;"ARCHITECTURE Behavioral OF BCD IS) signal I: STD_LOGIC_VECTOR(3 DOWNTO 0);, signal Segs: STD_LOGIC_VECTOR(6 DOWNTO 0);BEGIN PROCESS( i3, i2, i1, i0 ) BEGIN I(3) <= i3; I(2) <= i2; I(1) <= i1; I(0) <= i0;  END PROCESS;  bcd_comp: BCD_Vec port map( I => I,  Segs => Segs  );  a <= Segs(6); b <= Segs(5); c <= Segs(4); d <= Segs(3); e <= Segs(2); f <= Segs(1); g <= Segs(0); END Behavioral;.A 9z U3 T_030F3BE420041104012358DisplayGeneral$a9{L1T_04B22F4C20041104153934L_AX300_W100 (L)a9{L2T_09471BB020041104153937L_AX300_W100 (L)a9{L3T_04B50D4820041104153938L_AX300_W100 (L)a9{(L4T_04B2762020041104153940L_AX300_W100 (L)+9n8hU4T_075F79B420080901100911@9Y HT_02D766BC200410282346119Y HT_02D7695C200410282346119YpHT_02D76BFC200410282346119d@T_047FE8FC20041104012430 NOPCB (GND)5?t.@MbP??ư>&?Y@[dd??.A.A.AeAMbP?@@?{Gz?{Gz?$ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@";@ư>-q=ư>MbP?-q=MbP?vIh%<=Y@D@& .>?MbP?$@?{Gz?@??+= _B-q=$@Y@#B ;MbP??.A???Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%IT