Specifications

Theory of Operation

68000 microprocessor

The 68000 is the CPU of the system. All other resources are under software control via control data issued from it. All 3 custom chips have control registers that are written by the 68000.

The 68000 communicates with the rest of the computer via its address bus, data bus and control lines. Notice that in the block diagram the 3 custom chips do not reside directly on the 68000 busses. When the 68000 starts a bus cycle that is intended for the custom chips or the display RAM, the bus control chip detects whether or not the display RAM busses are available. The control chip will not assert the acknowledge signal (/DTACK) back to the 68000 until the display RAM busses are available. Once the 68000 receives /DTACK it completes the bus cycle. Connecting the display RAM busses to the 68000 busses is discussed further in the section bus control. Because the display RAM is capable of approximately twice the bandwidth of the 68000, the 68000 is usually not delayed by waiting for the display busses to become available.

The 68000 can fetch instrucions from:

    Display RAM
    ROM

The 68000 can read and write data directly to:

    Display RAM
    Parallel I/O chips
    3 Custom I.C.s
    ROM

The 68000 transmits data and control to and from the peripherals via the parallel I/O and the 3 custom chips.

/M is the processor clock to the 68000. C1, C3 and CDAC are used to clock the custom chips and determine the timing of signals to the memory arrays.

ROM

The ROM contains the kernel and DOS routines; it's 128Kx16.

Parallel I/O

The 2 multipurpose 8520 I/O chips provide the following:

I/O to and from the parallel port connector
Control lines to and from the joystick/mouse ports
A control line to the front panel LED
Internal control lines
Keyboard control lines, clock and data
Serial port control lines
Floppy disk interface control lines
Internal timers

Clocks Generator

The entire computer board is run synchonous to the 3.579545 MHz color clock.
This is accomplished by generating a number of submultiple frequencies from the master 28.63636 MHz NTSC (or 28.37516 MHz for PAL) crystal ascillator. All clocks are generated by the FAT AGNUS custom chip. The following are the primary clocks:

C1          3.579545 MHz color clock
C3          C2 shifted 45 degrees later
7M          C1 XORed with C3 = 7.15909 MHz
CDAC    7M shifted 90 degrees later
 

The 3 custom chips provide very fast manipulation of graphics and audio data in the display RAM. All the major functions in the chips are DMA driven; that is, streams of data are moved between the custom chips and display RAM under DMA control. These streams of data are acted upon by the custom chips. FAT AGNUS, custom chip #1, contains 25 dedicated purpose DMA counters.

The 3 chips have control registers which are usually loaded by the 68000. However, FAT AGNUS also has the capability of loading control registers in the other 2 custom chips. When FAT AGNUS performs a bus cycle, it outputs a code on the Register Address Bus telling the other 2 chips the nature of the bus cycle. This is necessary because many of the bus cycles provide data to or from the other 2 chips, thus must cooperate appropriately.

In addition to manipulating data in the display RAM, the custom chips output streams of data to the video output circuits and audio outputs circuits, and they move data to and from the floppy disks and serial port.

Note that the display RAM busses can be completely isolated from the 68000 busses by FAT AGNUS and Data Bus drivers. Thus, FAT AGNUS can be performing a bus cycle on the display busses simultaneously with the 68000 performing a bus cycle on its busses. This parallelism increases throughout.

Bus Control, Address/Data MUX, Address Driver

The bus control logic resides in the control chip (GARY) and FAT AGNUS. They provide 3 major functions, they:

Synchronize the 68000 to the current phase of C1
Arbitrate between the 68000 and FAT AGNUS for the display busses
Generate DRAM timing for the video RAM bus drivers appropriate to the current cycle.

Arbitration is very simple. FAT AGNUS tells the bus control prior to taking the display RAM busses by asserting an input to the control chip (GARY) called /DBR. Whenever FAT AGNUS has the display busses and the 68000 wants them, the 68000 is held off by not giving it /DTACK. In this state the 68000 has no effect on the display buses until the bus controller enables the bus drivers.

FAT AGNUS generates the DRAM timings and does all address multiplexing. If the 68000 is running a video memory cycle, its addresses are routed through FAT AGNUS onto the multiplexed address lines. If the custom chips are running a memory cycle the adresses are routed to the multiplexed address lines from internal address register.

Display RAM

The display RAM is a 512K read/write memory that resides on the RAM address and RAM data busses. It is expandable to 1MB by the addition of the RAM expansion module. It is implemented using standard 256Kx1 dynamic RAMs, refreshed by FAT AGNUS.

The display RAM is really used for much more than just holding graphics data. It also stores code and data for the 68000.

Custom Control Chips

The Amiga's animation, graphics and sound are produced by three custom chips. FAT AGNUS (8370), DENISE (8362) and PAULA (8364). A fourth custom chip, GARY serves as the control chip. Pin diagrams, feature lists and block diagrams can be found by clicking here. (under construction)