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Intel's high-end
desktops, workstations, and server processor
|
|
|
Clock
|
Transistors
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Bus width
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Pin count
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Package dimensions
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Addressable
memory
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Connector
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Introduced
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150
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5.5 million
(0.35 micron),
512K L2: 31 million
(0.35 micron)
256K L2: 15.5 million
(0.6 micron)
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64 bits front
side;
64 bits to L2
cache
|
387 (Dual Cavity
Pin Grid Array
Package)
|
2.46 (6.25cm) x 2.66
(6.76cm)
|
64
gigabytes
|
Socket
8
|
Nov1,
1995
|
|
166
|
5.5 million
(0.35 micron),
512K L2: 31 million
(0.35 micron)
256K L2: 15.5 million
(0.6 micron))
|
64 bits front
side;
64 bits to L2
cache
|
387 (Dual Cavity
Pin Grid Array
Package)
|
2.46 (6.25cm) x 2.66
(6.76cm)
|
64
gigabytes
|
Socket
8
|
Nov1,
1995
|
|
180
|
5.5 million
(0.35 micron),
512K L2: 31 million
(0.35 micron)
256K L2: 15.5 million
(0.6 micron)
|
64 bits front
side;
64 bits to L2
cache
|
387 (Dual Cavity
Pin Grid Array
Package)
|
2.46 (6.25cm) x 2.66
(6.76cm)
|
64
gigabytes
|
Socket
8
|
Nov1,
1995
|
|
200
|
5.5 million
(0.35 micron),
512K L2: 31 million
(0.35 micron)
256K L2: 15.5 million
(0.6 micron)
|
64 bits front
side;
64 bits to L2
cache
|
387 (Dual Cavity
Pin Grid Array
Package)
|
2.46 (6.25cm) x 2.66
(6.76cm)
|
64
gigabytes
|
Socket
8
|
Nov1,
1995
|
|
200
|
5.5million(0.35micron)
1mb L2 : 62 million
(0.35 micron)
|
300 bits
internal;
64 bits to
L2 cache
|
387 (Dual Cavity
Pin Grid Array
Package)
|
2.46 (6.25cm) x 2.66
(6.76cm)
|
64
gigabytes
|
Socket
8
|
Aug18,
1997
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