Chapter 3 
Sequential Logic Circuits

Objectives
At the end of this chapter, you should be able to:

1.	define what is a sequential circuit;

2.	draw the circuit diagram of an SR flip-flop and explain its function;

3.	draw the circuit diagram of a JK flip-flop and explain its function;

4.	explain the functions of D-type and T-type flip-flops;

5.	differentiate the functions of triggering control;

6.	identify the representations for different types of triggering in a circuit symbol; and

7.	explain the functions of direct inputs.

Reference
1.	Thomas C. Bartee, "Digital Computer Fundamentals," sixth edition, McGraw-Hill Publishing Company.

2.	Richard S. Sandige, "Modern Digital Design," McGraw-Hill Publishing Company.

3.	Theodore F. Bogart Jr., "Introduction to Digital Circuits,"” McGraw-Hill Publishing Company.

1 Introduction

Sequential logic circuits are those whose outputs depend on the state of inputs and the previous state of the outputs.  Because of this nature, they are able to remember a logic value.  There are several types of sequential logic circuits.  Some of them will be covered here.  They are flip-flops, counters, and shift registers.
2 Flip Flop

	A flip-flop is a bi-stable element which has two stable states, 1 or 0.  Therefore, a flip-flop can be used to store a digital value.  Same as other sequential logic circuits, the value stored in the flip-flop depends on the input and the previous value stored.  Due to this property, flip-flops are basic elements of a memory device in a digital computer.

	The outputs of the flip-flops are usually denoted by Q and .  In a stable state, the values of Q and  are complemented to each other.

	To understand the operations of flip-flops, several points must be noted.  First of all, a flip-flop is made with basic logic gates.  Therefore, one should be very familiar with the functions of these logic gates.  Secondly, the propagation delay of the logic gates must be considered.  Since the outputs are usually fed back to the inputs, the response in the outputs will happen some time after the inputs change.  In analyzing the circuit operations, the previous values of the output are taken to deduce the new output values.  Thirdly, the values of the two outputs, Q and , change in response to the change of inputs.  The changes may trigger another sequence of changes.  It takes time for them to settle to a stable state.  This values of the stabled outputs are taken as the final values.  Finally, in deducing the new values of the outputs, an initial value must be assigned to the previous outputs.  The initial value of an output can be either 1 or  0.  The value of the other output is therefore the complement of the first.  We usually use the symbol  to denote the initial (or previous) value of the Q output and  to denote the new value of the stable output Q.
2.1 S-R (Set-Reset) Flip Flop

	There are several types of flip-flops.  S-R flip-flop is the simplest one.  It can be made by any logic gates.  Figure 3.1 is an S-R flip-flop circuit made with NOR gates only.

Figure.3.1 S-R flip-flop with NOR gates.	

	The flip-flop consists of two inputs, S and R, and two outputs, Q and .  From the circuit configuration, we have:
 = 	(Eq. 3.1)
 = 	(Eq. 3.2)

	To understand its operations, we consider the four conditions of the inputs.  Each case, we have to look at the two possibilities: Q being 1 or Q being 0 initially.

	Case 1:	S = R = 0.
Assume = 0 and  = 1.  Substituting all the values into equation 3.1 and 3.2, we can find the new output values:  = 0 and  = 1.  However, if initially, = 1 and  = 0, the new outputs are:  = 1 and  = 0.  Therefore, we can conclude that the outputs, Q and , are unchanged if both inputs are 0.

	Case 2:	S = 0, R = 1.
Assume = 0 and  = 1.  Substituting all the values into equation 3.1and 3.2, we can find the new output values:  = 0 and  = 1.  If we assume= 1 and  = 0 as the initial state, the new outputs will be:  = 0 and  = 0.  This is not a stable state.  We have to substitute the values to the equations and find the new values of the outputs until the outputs settle to a stable state.  To better illustrate the changes, a timing table is used:

	t0	t1	t2	t3	t4	
S	0	0	0	0	0	
R	1	1	1	1	1	
Q	1	0	0	0	0	
	0	0	1	1	1	
Table 3.1. 

A timing table is similar to a timing diagram except in a table form.  The time sequence starts from left to right.  Adjacent columns represent a time interval, the propagation delay of a logic gate.  The table shows all the values of the inputs and outputs at different time.  The initial values are values at time t0.  The values of a logic gate output at time tn is determined by the value of the gate inputs at time tn-1.

From the timing table in table 3.1,  we can see that the outputs Q and  settle at time t3.  Their values are 0 and 1 respectively.  Therefore, we can conclude that the output Q is reset to 0 when the S is 0 and R is 1.

	Case 3:	S = 1; R = 0.
If initially, = 0 and  = 1.  Substituting all the values into equation 3.1and 3.2, the new output values are:  = 0 and  = 0.  Therefore, we have to use the timing table again to find the output values at the stable state.

	t0	t1	t2	t3	t4	
S	1	1	1	1	1	
R	0	0	0	0	0	
Q	0	0	1	1	1	
	1	0	0	0	0	
Table 3.2.

In table 3.2, we can see that the values of the Q and  settle at time t3 and their values are 1 and 0 respectively.

If we assume  = 1 and  = 0 as the initial state, the new outputs are still the same:  = 1 and  = 0.  Therefore, we can conclude that the output Q is set to 1 when the S is 1 and R is 0.

	Case 4:	S = 1; R = 1.
Since both inputs are 1, the outputs will be all 0 no matter what their initial values are.  If then, the inputs are all reset to 0, race happens between the two logic gates.  Because no two logic gates have the same propagation delay, eventually, one of the outputs will be 1 and the other 0.  However, which one is 1 cannot be determined.  Therefore, this case will never happen in a practical circuit.  The circuit designer makes sure this in designing a digital circuit.

	The whole operations can be summarized by a truth table (table 3.3):

S	R	Qn+1	
0	0	Qn	
0	1	0	
1	0	1	
1	1	Not used	
Table 3.3			

	An S-R flip-flop can also be constructed by NAND gates only.  Figure 3.2 shows an S-R flip-flop using NAND gates.

Figure.3.2 S-R flip-flop with NAND gates.	

	The operation of this flip-flop is similar to that built with NOR gates.  We have to consider the four different cases of input values.  For each case, the initial value of Q can be either 1 or 0.  However, the values of S and R inputs are inverted before they are fed into the flip-flop.
2.2 J-K Flip Flop

	The disadvantage of the S-R flip-flop is that only three cases of inputs are used.  Because an S-R flip-flop cannot be inputted a ‘1’ at its S and R inputs at the same time, application of the S-R flip-flop is limited.

	The J-K flip-flop is designed to overcome such limitation. Figure 3.3 is a J-K flip-flop built with NAND gates only.

Figure.3.3 J-K flip-flop with NAND gates.	

	According to figure 3.3, if we use G1 and G2 to denote the outputs of the gates G1 and G2 respectively, we have:

G1 = 	(Eq. 3.3)
G2 = 	(Eq. 3.4)
 = 	(Eq. 3.5)
 = 	(Eq. 3.6)

	Further investigation on figure 3.3, we can find that gates G3 and G4 form an S-R flip-flop (as in figure 3.2) with the  and  inputs being G1 and G2 respectively.  To understand the operations of the J-K flip-flop, we will investigate the outputs under different combinations of inputs:

Case 1:	J = 0; K = 0.
When both inputs are 0, the outputs of the gates G1 and G2, G1 and G2, will be 1 regardless the values of Q and .  Therefore, the outputs Q and  will remain unchanged.

	Case 2:	J = 0; K = 1.
There are two different possibilities: Q initially being 0 or 1.  In both situations, the values of G1 and G2 are both 1 because the outputs are at stable states.

If initially, Q is 0 and  is 1,  substituting all the values (J, K, G1, G2, Q and ) into the equations Eq.3.3 to Eq.3.6, we can find the values of G1, G2, Q and .  Their values are 1, 1, 0, and 1 respectively which are the same as their initial values.

However, if initially, Q is 1 and  is 0, the changes in the logic gates must be analysed with the aid of the following timing table (Table 3.4).  

	t0	t1	t2	t3	t4	t5	
J	0	0	0	0	0	0	
K	1	1	1	1	1	1	
G1	1	1	1	1	1	1	
G2	1	0	0	0	1	1	
Q	1	1	1	0	0	0	
	0	0	1	1	1	1	
Table 3.4.

In table 3.4, we find that the stable values of G1, G2, Q and  are 1, 1, 0, and 1 respectively.  From the above analysis, we can conclude that the outputs Q and  will be 0 and 1 respectively regardless their initial values if the inputs J and K are 0 and 1 respectively.

	Case 3:	J = 1; K = 0.
The analysis of this case is similar to that of the case 2.  Initially, the values of G1 and G2 are both 1 and the value of  Q  can be either 0 or 1.  Substituting all the values (J, K, G1, G2, Q and ) into the equations Eq.3.3 to Eq.3.6, we will find the stable values of the outputs.

In the situation that Q is 0 and  is 1 initially, the changes in the logic gates must be analysed with the aid of the following timing table (Table 3.5).  

	t0	t1	t2	t3	t4	t5	
J	1	1	1	1	1	1	
K	0	0	0	0	0	0	
G1	1	0	0	0	1	1	
G2	1	1	1	1	1	1	
Q	0	0	1	1	1	1	
	1	1	1	0	0	0	
Table 3.5.

In table 3.5, we find that the stable values of G1, G2, Q and  are 1, 1, 1, and 0 respectively.

If initially Q is 1 and  is 0, we can find the values of G1, G2, Q and  are unchanged, i.e. their values are 1, 1, 0, and 1 respectively.

From the above analysis, we can conclude that the outputs Q and  will be 1 and 0 respectively regardless their initial values if the inputs J and K are 1 and 0 respectively.

	Case 4:	J = 1; K = 1.
Analysis of this case must make use of the timing table.  Table 3.6 shows the changes in the outputs of the four logic gates when the inputs are changed.

	t0	t1	t2	t3	t4	t5	t6	
J	1	1	1	1	1	1	1	
K	1	1	1	1	1	1	1	
G1	1	0	0	0	1	0	0	
G2	1	1	1	0	0	0	1	
Q	0	0	1	1	1	0	1	
	1	1	1	0	1	1	1	
Table 3.6.

It seems that, in Table 3.6, the outputs will never settle to a stable state.  However, if we look at the timing table more carefully, we will find that the output values at t6 are same as that at t2.  That means the outputs will repeat the changing patterns every four time intervals if we maintain the inputs at 1 constantly.  This is the real situation how the inputs affect the outputs: setting both J and K inputs at 1 indefinitely will make the outputs change indefinitely.

However, if we want to investigate the effects of the changes in inputs, we can do the following steps: setting both J and K to 1 so that the changes have the effect on the outputs (2 propagation delay time required), then resetting both J and K to 0 which makes the output settle.  The changes will be shown on the timing table 3.7.
	
	t0	t1	t2	t3	t4	
J	1	1	0	0	0	
K	1	1	0	0	0	
G1	1	0	0	1	1	
G2	1	1	1	1	1	
Q	0	0	1	1	1	
	1	1	1	0	0	
Table 3.7.

From table 3.7, we can see the real effect of the inputs in case both J and K are 1 which makes the output change from 0 to 1 ( = 0).  Should the initial value of Q being 1, the readers can find that a logical 1 appearing at both J and K inputs will make the Q change to 0.

	The following truth table, therefore, summarizes the different conditions:

J	K		
0	0		
0	1	0	
1	0	1	
1	1		
Table 3.8.

	A J-K flip-flop can also be constructed by NOR gates only.  Figure 3.4 is the circuit.
	
Figure.3.4 J-K flip-flop built with NOR gates.	

	The operations of this J-K flip-flop can be analyzed with the same methods.  This is left as an exercise for the readers.  Readers can find the same truth table in table 3.8.

	Similar to the different logic gates, there are different circuit symbols for the flip-flops.  Figure 3.5 shows the symbols of the S-R and J-K flip-flops.

a. S-R flip-flop.	b. J-K flip-flop.	
Figure 3.5.  Circuit symbols of basic flip-flops.	

2.3 D-type and T-type Flip-Flop

	Other than S-R flip-flop and J-K flip-flop, two other types of flip-flops are also commonly used.  They are D-type flip-flop and T-type flip-flop.  These flip-flops are usually edge-triggered flip-flops.

	The circuit symbols and the truth tables of the D-type flip-flop and T-type flip-flop are given in Figure 3.6 and Table 3.9 respectively. 
		
a. D-type flip-flop.	b. T-type flip-flop.	
Figure 3.6.  Circuit symbols.	

D			T		
0	0		0		
1	1		1	Toggle	
Table 3.9  Truth table of the D-type and T-type flip-flops	

2.4 Triggering of flip-flop

	Given a change in the inputs of a flip-flop, we can forecast its response at the output according to its truth table.  If we put all these in a graph showing all the changes with respect to the time, we will have a timing diagram as in figure 3.7.  The time scale in a timing diagram is relatively large compared with that in a timing table.  The time interval in a timing table is one propagation delay of a logic gate which is in the scale of nano-second (10-9 Sec).  However, in a timing diagram, the time scale is in the scale of mini-second (10-3 Sec).  For this reason, changes in the input will reflect in the output almost immediately.  Readers should bear in mind that certain delay may arise in real cases although we cannot notice that.

Figure.3.7 A timing diagram of the S-R flip-flop.	

	The variation in the inputs and outputs in the timing diagram is called waveform.

	The output of a flip-flop is triggered by the changes in its inputs.  Because the triggering has immediate effect on the output, should there be any unwanted situation happens, i.e. 1 appearing at both S and R inputs, the output will be out of control.  Therefore, we need a certain control on this triggering. The simplest way to control the trigger is to use a clock signal which allows the triggering to happen only when both the inputs are stable and under predictable conditions.

	The clock signal usually consists of a series of pulses.  A sample clock signal is given in figure 3.8.

Figure.3.8 A clock signal.	

	There are different ways to apply the clock to control a flip-flop, namely level-triggered (clocked) and edge-triggered.  A flip-flop responses to the input changes when the clock is at logical 1 is called a positive clocked (positive level-triggered) flip-flop.  Similarly, a negative clocked (negative level-triggered) flip-flop responses to the input changes when the clock is at logical 0.

	A flip-flop responses to the input changes when the clock changes from logical 0 to logical 1 is called a positive edge-triggered flip-flop.  Similarly, a negative edge-triggered flip-flop responses to the input changes when the clock changes from logical 1 to logical 0.

The truth tables in table 3.10 show the operations of the positive clocked flip-flops.
Clk	S	R			Clk	J	K		
0	X	X			0	X	X		
1	0	0			1	0	0		
1	0	1	0		1	0	1	0	
1	1	0	1		1	1	0	1	
1	1	1	Not used		1	1	1		

Clk	D			Clk	T		
0	X			0	X		
1	0	0		1	0		
1	1	1		1	1		

Table 3.10  Truth tables of the positive clocked flip-flops.

	Symbols of the clocked flip-flops are somewhat different from that of the basic flip-flops because an extra input terminal exists.  Figure 3.9 shows the circuit symbols of the positive clocked flip-flops.  They are named positive clocked flip-flops because the inputs trigger the output when the clock is at logical 1.

a. Positive clocked S-R flip-flop.	b. Positive clocked J-K flip-flop.	
		
c. Positive clocked D-type flip-flop.	d. Positive clocked T-type flip-flop.	
Figure 3.9.  Circuit symbols of positive clocked flip-flops.	

	If the inputs trigger the output only when the clock is at logical 0, the kind of flip-flops are called negative clocked flip-flops.  The truth tables of the negative clocked flip-flops are given in table 3.11.

Clk	S	R			Clk	J	K		
0	0	0			0	0	0		
0	0	1	0		0	0	1	0	
0	1	0	1		0	1	0	1	
0	1	1	Not used		0	1	1		
1	X	X			1	X	X		

Clk	D			Clk	T		
0	0	0		0	0		
0	1	1		0	1		
1	X			1	X		

Table 3.11  Truth table of the negative clocked flip-flops.

Figure 3.10 shows the symbols of the negative clocked flip-flops.

a. Negative clocked S-R flip-flop.	b. Negative clocked J-K flip-flop.	
		
c. Negative clocked D-type flip-flop.	d. Negative clocked T-type flip-flop.	
Figure 3.10 Symbols of negative clocked flip-flops.	

	One can expect that the inputs of a clocked flip-flop, either positive or negative clocked flip-flop, must be ready before the clocked period and remain unchanged for the whole period.  For example, the waveforms in figure 3.11 show how to use the clock signal to control the operations of a positive clocked S-R flip-flop.
	
Figure.3.11 Sample waveforms of the inputs and outputs of a positive clocked S-R flip-flop.	

	Notice that, in figure 3.11, changes of inputs S and R take place when the clock is at logical 0.  This is because the flip-flop responses to the inputs only when the clock is at logical 1.

	Look at the other example in figure 3.12 which shows the waveforms in a negative clocked J-K flip-flop.
	
Figure.3.12 Sample waveforms of the inputs and outputs of a negative clocked J-K flip-flop.	

	In figure 3.12, the output changes according to the inputs only when the clock is at logical 0 because the flip-flop is now negative-clocked.  Notice that at the fourth clocked period, both J and K inputs are at logical 1.  The output Q therefore oscillates between 1 and 0 during the whole period.  This is because both J and K are at logical 1 for a relative long time which has been analyzed in the timing table, table 3.6.
		
a. Positive edge-triggered S-R flip-flop.	b. Negative edge-triggered S-R flip-flop.	
		
c. Positive edge-triggered J-K flip-flop.	d.  Negative edge-triggered J-K flip-flop.	
		
e. Positive edge-triggered D-type flip-flop.	f.  Negative edge-triggered D-type flip-flop.	
		
g. Positive edge-triggered T-type flip-flop.	h.  Negative edge-triggered T-type flip-flop.	
Figure 3.13 Circuit symbols of edge-triggered flip-flops.	

	Although we want the outputs to respond to this case of inputs, i.e. J and K being both 1, we do not want it to oscillate.  If this happens, at the end of the clocked period, we do not know exactly what the outputs will be.  In order to overcome such drawback, additional circuits are therefore designed so that the outputs of a flip-flop respond to the inputs only when the clock changes.

	The edge-triggered flip-flops serve this function.  There are two types of edge-triggered flip-flops.  Positive edge-triggered flip-flops change state at the time the clock changes from 0 to 1.  Negative edge-triggered flip-flops change states at the time the clock changes from 1 to 0.  Several methods can be used to configure these flip-flops.  However, these configurations are rather complicated and we will not go into the details of this.  We will concentrate on how the outputs response when these flip-flops are used.

	The circuit symbols of the different edge-triggered flip-flops are given in figure 3.13.

	The truth tables for the edge triggered flip-flops are given in Table 3.12 and Table 3.13.

Clk	S	R			Clk	J	K		
	0	0				0	0		
	0	1	0			0	1	0	
	1	0	1			1	0	1	
	1	1	Not used			1	1		

Clk	D			Clk	T		
	0	0			0		
	1	1			1		
Table 3.12 Truth tables of the positive edge-triggered flip-flops.

Clk	S	R			Clk	J	K		
	0	0				0	0		
	0	1	0			0	1	0	
	1	0	1			1	0	1	
	1	1	Not used			1	1		

Clk	D			Clk	T		
	0	0			0		
	1	1			1		
Table 3.13 Truth table of the negative edge-triggered flip-flops.

	When applying the inputs to the edge-triggered flip-flops, the inputs must be stable before the clock transition happens.  Figure 3.14 shows how the output of a negative edge-triggered J-K flip-flop response to the same inputs as in figure 3.12.

	In figure 3.14, the output only changes when the clock changes from 1 to 0.  During the whole clock period, be it at 1 or 0, the output will remain unchanged.

Figure.3.14 Sample waveforms of the inputs and outputs of a negative edge-triggered J-K flip-flop.	

Figure.3.15 Sample waveforms of the outputs of different types of J-K flip-flops in responding to same inputs.	

	Figure 3.15 shows how the outputs of different types of J-K flip-flops in responding the same inputs.
2.5 Direct inputs

	Some of the flip-flops facilitate direct inputs so that the state of a flip-flop can be directly assigned by these direct inputs.

	Figure 3.16 shows the circuit symbols for a negative edge-triggered J-K flip-flop with direct preset and clear inputs. The Q output will be set to logical 1 if PS, preset, is 0.  If Clr, clear, is 0, Q output will be reset to 0.
	
Figure.3.16 Negative edge-triggered J-K flip-flop with direct inputs.	

	Under normal operation, both direct inputs, preset and clear, are at logical 1.  However, they cannot be both set to 0 because this happened, the output would be undetermined.

	Notice that the circles in the direct inputs in figure 3.16 indicate the preset and clear functions are low-activated, i.e. a logical 0 triggers the function.  A high-activated direct input functions require a logical 1 to trigger the action.  The symbols of the flip-flops with high-activated direct inputs will have no circles on the direct input terminals.