by: Mr. Rodelio
P. Barcenas
Faculty Computer Engineering
Department
Don Bosco Technical College
Last Example:
The circuit below contains four
(4) registers namely A,B,C, and G. Each register has four (4) bit
output lines. Let us take for example reg. A for discussion. Register
A contains output lines A0, A1, A2, A3. The four variables are members
of set A. If register A has a value of 7, A3 = 0, A2 = 1, A1 = 1,
and A0 = 1. The registers also functions as a data loader using variable
L.
The multiplexer has 2 input lines,
S1, and S0. The multiplexer behaves in these condition;
- If S = 0 {S1 = 0, S0 = 0} ; then
y = a
- If S = 1 {S1 = 0, S0 = 1} ; then
y = b
- If S = 2 {S1 = 1, S0 = 0} ; then
y = c
- If S = 3 {S1 = 1, S0 = 1} ; then
y = d
The 2 x 4 decoder has the following
conditions;
- If X = 0; L1 = 1
- If X = 1; L2 = 1
- If X = 2; L3 = 1
- If X = 3; L4 = 1
In order to reproduce the RTL of the
above circuit, we have to identify the control elements first. It
can easily be seen that the control elements would be X1, X0, S1,
and S0. We have a four (4) bit control element and that will make
16 possible combinations of 1s and 0s. To state it in another way,
the circuit above contains 16 RTLs.
This is the list of RTLs for the above
circuit.
X1'X0'S1'S0': A <-- A
X1'X0'S1'S0 : A <-- B
X1'X0'S1 S0': A <-- C
X1'X0'S1 S0 : A <-- G
X1'X0 S1'S0': B <-- A
X1'X0 S1'S0 : B <-- B
X1'X0 S1 S0': B <-- C
X1'X0 S1 S0 : B <-- G
X1 X0'S1'S0': C <-- A
X1 X0'S1'S0 : C <-- B
X1 X0'S1 S0': C <-- C
X1 X0'S1 S0 : C <-- G
X1 X0 S1'S0': G <-- A
X1 X0 S1'S0 : G <-- B
X1 X0 S1 S0': G <-- C
X1 X0 S1 S0 : G <-- G
At this point, you might be wondering
where are we going? The RTLs are now getting longer and longer.
Well, I promise the next page will give you all the answers you've
been waiting for.
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