MKTREE — Auto-Connects Verilog!

MKTREE automatically connects Verilog modules, swiftly and accurately generating the tedious port—net lists. Changing module partitioning or re–using modules between projects is a snap, as MKTREE instantly builds new interconnect files for you.

Expanded Example click here.

• Used to Develop Working Silicon
• In-use by Major Multi-National Companies
• Allows FAST Hierarchy & Partition Changes
• Written in C for Performance
• Able to Handle LARGE Designs
• Assists in Design Documentation
• Easy to use
• Support and Customization Available

MKTREE solves problems associated with manually connecting Verilog modules. With MKTREE, the designer specifies the high–level module hierarchy in a treefile. MKTREE automatically generates the Verilog interconnect files with all of the port—net pairs listed for each instantiation.

Silicon-proven, MKTREE is used by major multinational corporations and has built large single–chip PC designs.

Using MKTREE eliminates the time–consuming and error-prone burden of manually listing the port—net pairs. The designer only needs to list the signals that change names when the associated module is instantiated.

The treefile is simpler to write and maintain than the Verilog interconnect files and provides a excellent high–level view of the design that is easier to understand and reconfigure than the common labor–intensive approach.

Changing module hierarchy or re–using existing blocks is fast and accurate with MKTREE. Whenever bus–widths or signal names change, MKTREE rebuilds the interconnect files in a matter of seconds.

MKTREE also checks the wiring of your design and immediately reports all driver conflicts and dangling single–connect wires.

As an example, the following portion of a treefile automatically creates a memory module with two data memory blocks and two parity memory blocks:

        demo_mem
        {
                demo_ram        bank1   (sel=cs[0]);                    
                demo_parity     parity1 (sel=cs[0]); 
                demo_ram        bank2   (sel=cs[1]);
                demo_parity     parity2 (sel=cs[1]);
        }

Note that the only signals specified are those that changed names across the port—net boundary. All other signals retained their names and were automatically connected by MKTREE.

The files generated by MKTREE are ordinary Verilog text files and can be stored in a code control system, delivered with the design files, or edited. Scripts can be written to further customize the generated files.

Each generated file has a header that can easily be changed to match the any methodology or coding standard. The headers can be formatted to include a wide variety of date and time information, filename, module name, and user name.

To see a more detailed, but still very simple, example, click here.

MKTREE has been retrofitted into existing traditional designs and has been integrated into new developments.