Curriculum Vitae NAME: Vishal Dalal FATHER'S NAME: Shri Prakash Dalal DATE OF BIRTH: March 27, 1976 EDUCATIONAL QUALIFICATION: Master of Technology in VDTT (VLSI Design Tools and Technology) from Indian Institute of Technology, Delhi, January 2000 WORK EXPERIENCE: 3 years on Feburary 21, 2003 AREAS OF INTEREST: Front End VLSI Design, Verification and Synthesis, Networks, Processors, Low Power/High performance designs PUBLICATIONS: 1. "3C's in an SOC Verification", CADENCE ICON News letter, November 2002 2. 6th IEEE VLSI Design and Test Workshops (VDAT), "System Level Verification of Present System on Chip(SOC)",August 2002, Bangalore, India 3. 5th IEEE VLSI Design and Test Workshops (VDAT), "Verification of multi-million GATE ASIC's", August 2001, Bangalore, India 4. 14th International Conference on VLSI Design, "Software Power Optimizations in an Embedded System", January 2001, Bangalore, India (see Abstract below) 5. "Reusability and Modularity in SOC Verification", Vishal Dalal & Achutha Jois, IP Based SOC Design, October 2002, Grenoble, FRANCE E-MAIL: vishaldalal@mailcity.com, dalal_vishal@hotmail.com PERMANENT ADDRESS: 2953, "Anugraham", 6th Cross, 19th main, HAL-II stage, Indiranagar, Bangalore-560008 PHONE NUMBER: +91-80-5277537 (HOME) MARITAL STATUS: Married EDUCATIONAL BACKGROUND: DEGREES: B.E. (Electronics & Comm) Institute: G.E.C, Ujjain Year: 1997 Percentage: 81.3% M.Tech. (VDTT) Institute: IIT, Delhi Year: Jan 2000 CGPA: 7.67/10 WORK EXPERIENCE: Working as an Senior Design Engineer in SASKEN Communication Technologies Limited, Ring Road, Domlur,Bangalore (India), since Feb. 21, 2000 Phone: +91-80-5355501/03, Extn: 8306 Current Project Presently involved in the Verification of an SOC for next generation cable modems. The project has commenced from March. 2003 with TI Israel as the customer.This is the next version of my earlier project, PUMA-S. The modules to be verified now are USB(2.0), VLYNQ etc. The system level verification is done by using Specman and Seamless Co-verification tools. NCSIM simulator will be used for Gate level verification. Projects Done: 1. Completed working on System Level (Chip Level) verification of a multi-million GATE SOC, "PUMA-S", on Feb. 15, 2003, with TI, Israel as the customer. This was a broad-band network controller destined to be used in cable modems and expected to churn big revenues for TI. It implements DOCSIS2.0 standards. The work involved writing/modifying the chip level test cases (written in "C" and "e" language) to verify inter-working of various modules like VLINK, TIMER, I2C etc at System level. I was completely responsible for above modules. The work also included verifying the test cases on VMC model of the MIPS processor. The project also involved the verification at the GATE level by doing gate level simulations using IKOS accelerator tool (Mentor) and NCSIM. The GATE level verification was done on complete chip level net-list back annotated with SDF (Post-layout). Duration: One year two months Tools used: The verification environment consist of SPECMAN ELITE tool along with Hardware-Software co-verification Environment of Seamless (from Mentor Graphics). The simulator used is NCSIM. For GATE level verification, IKOS tool is used along with NCSIM. 2 System Level Functional Coverage of OMAP (Open Multi Media Application Platform) Chip. Customer: Texas Instruments, Bangalore, India Work Description: The project involved writing functional coverage monitors at the System level for the complete OMAP chip. The aim was to trace all the control and data paths meshing the whole chip and see if the necessary transitions in the corresponding signals are happening to cover communication between various modules. A large number of coverage monitors were written for the same. Duration: 4 months Tools Used: Modelsim 3. Module level verification of McBSP module of JANUS chip Customer: Texas Instruments, Houston, Texas, USA Work Description: The work involved functional verification of McBSP(Multi Channel Buffered Serial Port) module by writing checkers. Duration: 4 months Tools used: Specman-Elite (Verisity), Modelsim Language used: e language, VHDL 4. RTL Verification of Scaler module of OHIO Chip Work Description: The work involved verifying the Scaler module at RTL level by writing different test cases and running the simulations. Duration: 2 months Tools Used: CADENCE AFFIRMA Simulator Language Used: VHDL 5. Reference Design for 3G mobile phones Work Description: The work was to develop reference design for 3G physical layer. I joined the project from the start. I was completely responsible for the critical RTOS part of the design. Later I developed terminal controller for communication between application and reference design. I was also involved in the setting up of Strong ARM evaluation board. Duration: 7 months Tools Used: Tornado Tools for VxWorks Language Used: TCL/Tk MASTERS PROJECT: "Software Power Optimizations in an Embedded system", guided by Prof. C. P. Ravikumar. Abstract The topic of reducing power dissipation in an embedded system has received considerable attention in the recent years. Techniques have been reported to minimize energy dissipation through (a) selection of better algorithms for the application e.g. DSP algorithms that require fewer number of operations to perform a task such as filtering (b) minimizing state transitions and switching activity in the hardware implementation, and (c) reducing the operating supply voltage by changing the architecture of the system e.g. through the use of pipelining. However, power dissipation is often neglected when developing the software for embedded systems. Software optimization techniques can be used to reduce the cost, size and power dissipation in embedded systems without adding to system overheads. In this paper, we view the power dissipation as consisting of two parts, the power dissipated in the application-specific integrated circuits (Hardware Power) and the power dissipated by the CPU, memory and associated buses (Software Power). We provide a trace-based technique to estimate software power and study the effect of different code optimization techniques on software power, performance and code size. MASTERS SUBJECTS: CAD of Digital Systems, CAD of VLSI, DSP, MOS LSI, Testing and Fault Tolerance, Microelectronics SOFTWARE SKILLS: * Languages: e language (Verisity), C, VHDL, Verilog, Assembly Language of ARM * Operating Systems: UNIX(HP-9000, SUN), WINDOWS and WINDOWS NT, * Real Time Operating Systems(RTOS): Vx-Works * Scripting Language: PERL TOOLS WORKED ON: * Specman Elite (Verisity) * Formality, IKOS accelerator * Seamless (Mentor Graphics) * Simulators: Modelsim, NCSIM Simulator * Prime Time, Design Compiler (Synopsys) * ARM Software Development Toolkit (SDT), Tornado Tools for VxWorks * Tanner tools for circuit simulations like T-Spice, S-Edit, L-Edit TRAININGS/CONFERENCES ATTENDED: 1. Attended (as a speaker) the 14th International Conference on VLSI Design, January 3-7, 2001, Bangalore 2. Central Electronic Engineering Research Institute(CEERI), Pilani, Rajasthan from 10 May 1999 - 25 May 1999. The training was aimed to expose various processes involved in IC fabrication like oxidation, masking etc. ACHIEVEMENTS: 1. GATE (Graduate Aptitude Test of Engineering) 1998, 98.30 percentile 2. Selected in PGDIE (Post Graduate Diploma in Industrial Engineering),NITIE, Mumbai 3. President Speak@SASKEN toastmasters club NATIONALITY: Indian LANGUAGE KNOWN: Can efficiently communicate in English and Hindi HOBBIES: Reading, Writing, Meditation, Travelling and making friends REFERENCES: 1. Dr. C.P.Ravikumar, Texas Instruments, Bangalore e-mail: cpravikumar@hotmail.com, ravikumar@india.ti.com