Title: Verificatiopn of Multi-million GATE ASIC's
  By: Vishal Dalal (vishald@sasken.com)

The complexity of today's multi million ASIC's is increasing tremendously with more and more 
transistor's put on a single chip. Due to this, verification of the design has also become 
very demanding. Typically, design teams spent 50 to 70 percent of their time and resources 
in verifying the design. In fact it is said that as complexity of designs double the 
verification effort quadrapule. The time-to-market schedule constraint may force the 
verification to end prematurely without sufficient design coverage. This may lead to re-spins 
and subsequent redesigns further adding to the overall cost.  
	The verification methodology therefore needs to incorporate these rapidly changing 
scenarios to produce bug free chips and needs to be automated with an efficient and fast 
EDA tool. In this paper we deal with the problems faced in verification and there solutions. 
We discuss about various test methodologies and checking strategies. We also discuss various 
coverage metrics to measure and quantify the verification process. We have used the 
verification methodology provided by Verisity's Specman Elite as the baseline and how it 
solves the complex problems associated with verification. We briefly touch upon the e-language 
used by specman elite, constraint based generation, events and checkings.