Site hosted by Build your free website today!

Input Stage Distortion

Most published amplifier designs use a differential 'long-tailed-pair' input stage. This is partly because direct coupled outputs are used, so a low output offset voltage is needed, and the differential stage is used together with d.c. negative feedback to maintain a low offset. My own recent designs use capacitor coupling at the output, and this makes alternative input stages worth considering. My choice of a complementary feedback pair (cfp) input stage has not been explained yet, so here I present distortion calculations for most of the simplest input stages commonly used. More complex designs exist of course, but excellent results are possible with simple two transistor stages, and only these and single transistors are considered here.

Harmonic distortion calculations can be difficult, involving Bessel functions and so on, but there is an alternative very easy method of comparing linearity, which gives some indication of the level of intermodulation distortion produced. The idea is to start with a d.c. output of, for example, 1mA from the stage, and calculate the mutual conductance of the stage, gm. Then the value of gm is calculated for current increased or decreased by 10%. Ideally the value of gm will remain unchanged at different current outputs. If we imagine a low frequency signal large enough to give the +/- 10% output current, then changes in gm will change the gain for a lower level high frequency signal, and so the gm variations can be expected to be proportional to the peak intermodulation distortion generated. The big advantage of this method is that gm is very easy to calculate for both bipolar and fets. There are of course other distortion mechanisms in addition to gm variations, so these also must be taken into account in a practical design. Here just the gm effect is calculated.

The order of harmonic distortion is of some importance, and fets are sometimes used in the belief that these produce only second harmonic while bipolar junction transistors (bjts) generate higher order components. At low signal levels however bjts are almost as good as fets in this respect, depending on how the comparison is carried out. If, for example, we choose a signal level such that the second harmonic is at 1% then for the bjt third harmonic is at 0.0064%. Fets vary rather more than bjts, but one published measurement (Baxandall) suggests that at 1% 2nd there may be around 0.003% 3rd. Using an accurately balanced differential stage both types can cancel 2nd harmonic but 3rd and other odd harmonics are produced, so this advantage of fets is then lost. A perfect square law fet alone will generate only second harmonic distortion, but even then a pair used in a differential stage will generate third and higher harmonics.

A problem with comparing bjts with fets is that at 1mA current the values of gm are usually widely different. To compensate for this we could use a smaller input signal level for the bjt to give the same output current variation, or we could include a resistor in series with the emitter to give the same value of gm. Both of these are included to show which is better, though direct substitution for a fet in an input stage is generally only possible with the emitter resistor included.

The value of gm is accurately determined by the collector current for the bjt, but different types, or different samples of the same type of fet can vary over a wide range of gm at a given drain current. To enable the calculation to be done a 'typical' small-signal fet is chosen in which a 1 volt increase in gate-source voltage is required to increase drain current from 0 to 1mA. The results are therefore not necessarily the best possible performance for fet stages, and special high gm types such as the 2SK170 could include source resistors to improve linearity. The specification for this particular device however shows a range of Idss from 2.6 to 20mA, and typical gm at 3mA of 22mS, still less than a bjt.

The 7 different input stages are shown next.

A typical calculation, for diagram, A. The value of gm for a bjt is simply I/25 S where I is the collector current in mA. At 1mA therefore gm= 0.04 S. (The units of gm are 1S = 1 amp/volt.) At 1.1mA gm becomes 0.044 and at 0.9 mA it is 0.036. The value of gm is therefore increased by 10% at 1.1mA and decreased by 10% at 0.9mA.

For fig.G the result depends on the choice of base-emitter resistor of the pnp transistor, and also on its current gain, which was chosen to be around 200. The total current for the two devices is taken to be 1mA. The calculation is more difficult for this version, and I made the simplifying assumption that the current gain of the second transistor is constant, which in practice will depend on the transistor type. Results published by D.Self for a differential stage using two cfps are not as impressive as I would have expected. His tests appear to be at a higher signal level, and he compares with a circuit similar to my fig.D, but using the same value emitter resistors, only 22 ohms, rather than the same gm as in my comparison, which partly accounts for his result for the cfp, which even so was better by a factor of 8.

The results are as follows, showing the percentage change in gm for output collector or drain current changing from 1mA to 1.1mA or to 0.9mA. The differential stages have half the value of gm compared to the single devices. at at 0.9mA

From these results we can see that bjts with emitter resistors are more linear than the 'typical' fet with the same gm, that differential stages are far better than single devices, but the winner is the complementary feedback pair (cfp). The signs of the error percentages give some suggestion of the order of harmonic distortion. A, C, E and G have more even order distortion, widely agreed to be the least unpleasant, while B, D and F have mostly odd order, adding further advantage to G compared to its nearest challenger D. Further improvement to the cfp could be achieved by replacing the 6k resistor by a current source.

The two transistor differential stages need accurately matched currents for minimum distortion, and this can be achieved using a current mirror load using two transistors. The tail current needs to be a constant current source, and this adds at least one more transistor, so in practice D turns out to be at least a 5 transistor input stage, with higher distortion than the two transistor stage G.

The reason for comparing the input stages at +/- 10% current output is that usually this is the level giving 10% of the maximum output slew rate. Any well designed amplifier will have a maximum slew rate well above the maximum required by the music signal, and a factor of 10 seems a reasonable safety margin. Aiming for low distortion at the 10% level then ensures adequate performance with a normal music signal.

For higher output currents it is not necessary to repeat the calculations, we can easily estimate how the different stages behave. B, D and F generate mostly third harmonic distortion, and this will increase in proportion to the signal amplitude squared. A, C, E and G generate mostly second harmonic which will increase only in proportion to the amplitude. The cfp stage will therefore become even better compared to the differential stage D as the signal level is increased. Had we chosen a much lower output than the +/- 10% , the cfp would not have been the best numerically, although the lower audibility of second harmonic compared to third should be taken into account.

Using high gm fets or bjts with an added resistor in series with source or emitter will add noise. All resistors generate thermal noise proportional to the square root of the resistance, and any resistance effectively in series with the input signal will therefore worsen the signal to noise ratio, but the total noise voltage in series with the emitter or source is greater than expected if the external resistor alone were the only noise source. It is known that for a bjt there is an extra equivalent noise resistance in series with the emitter with value 0.5/gm. Whether something similar happens for fets is perhaps less well known, but rather than search for information on this point I consulted the data sheet for the 2SK170, and sure enough the noise voltage graph shows a value rising as drain current is reduced and consequently 1/gm increases. The increase appears to be equivalent to a resistance of around 0.8/gm, which if correct suggests that this fet has more noise added by the gm effect than a bjt with the same gm. Using a bjt with series resistor may add more noise resistance than a fet without series resistor and the same total gm, but the difference can be expected to be small. The added noise voltage, being a square root function of the resistance, will then differ very little. In power amplifiers noise is not usually a serious problem, so a small difference between these fets and bjts is nothing to worry about, and in any case the input noise voltage and current of the devices must be included in the total noise figure, which may in some cases reverse the result of the bjt-fet comparison. Power amplifiers are usually driven from a fairly low impedance, and input noise current is then not too important, but in other applications this may become a deciding factor.

The 2SK170 and some other high gm fets are about 10 times the price of good low noise bjts. Compared to the 2SC2547 bjt the 2SK170 fet has typically twice the noise voltage, twice the feedback capacitance, and a 5th of the gm at 3mA. Fets have some advantages, e.g. very low input current at d.c. and low frequencies, and the full data should of course be consulted to determine which device is most suitable for any given operating conditions. The 2SK170 is an N-channel jfet, the P-channel version is the 2SJ74, a dual matched pair N-channel is the 2SK389, and dual P-channel 2SJ109.

The analysis of the cfp stage made the assumption that the npn second device has a constant current gain. Looking at the graphs of current gain vs collector current in the Motorola 'European Home Electronics Data Book' most of the low power transistors have maximum gain around 10 to 20mA. With the 1mA current chosen for the cfp stage the gain will be increasing with current, and this will add to the distortion from other sources of non-linearity. What we need is a device with either constant current gain at 1mA +/- 10% or even better a reducing gain with increased current so that other non-linearity can be partly cancelled. The best I found so far is the BC650 (or the higher voltage BC651) which has maximum d.c. current gain around 1mA, but unfortunately appears to no longer be available. Another alternative is the 2SC2911 which has an almost flat current gain from under 1mA up to 30mA, but this is a medium power device with lower gain.


The distortion from gm variations in input stages becomes less of a problem as negative feedback is increased. To see why this is so consider my MJR7 circuit, which has open-loop gain around 200,000 up to 3kHz. For a 1V input and a 20V output the a.c. signal at the base of the input transistor will be about 100uV. Suppose we instead used a circuit with no overall feedback, then the input stage will need to handle the full 1V input signal. Many of the distortion mechanisms such as TID, PIM etc which are said to be consequences of overall negative feedback are primarily determined by input stage nonlinearity, but achieving high linearity in the input stage is far easier if it only needs to handle a hundred microvolts.
As an example suppose we used the worst of the input stages analysed here, the single bjt. At 100uV input the distortion will be about 0.1%, almost entirely second harmonic. Add 80dB overall negative feedback and the distortion from the input stage drops to around -140dB, still mostly second harmonic, so even the worst input stage is not bad. Other problems may still be important, e.g. common-mode distortion, Early effect distortion and so on, which is why my amplifier designs do not just rely on high feedback, but also use the inverting 'virtual earth' configuration and a cascode stage. Using the better cfp input stage it is then possible to trade some of the linearity for increased input stage gain so that the whole 200,000 gain can be achieved with just this input stage plus cascode, keeping the overall circuit relatively simple.