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Department of Computer Science, UMass Amherst Andrew H. Fagg

STS 107-S

CMPSCI 377: Operating Systems Lecture 2, Page 1

Department of Computer Science, UMass Amherst Andrew H. Fagg

Announcements/Reminders

² Handout from Friday available from the web site

² Lab 0 due Wednesday

² checkhw and java/javac are working on the EdLab machines

CMPSCI 377: Operating Systems Lecture 2, Page 2

Department of Computer Science, UMass Amherst Andrew H. Fagg

Last Class: Introduction to Operating Systems

User Applications

Virtual Machine Interface

Physical Machine Interface

Hardware

Operating System

² An operating system is the interface between the user and the

architecture.

{ History lesson in change.

{ OS reacts to changes in hardware, and can motivate changes.

CMPSCI 377: Operating Systems Lecture 2, Page 3

Department of Computer Science, UMass Amherst Andrew H. Fagg

Today: OS and Computer Architecture

² Basic OS Functionality

² Basic Architecture reminder

² What the OS can do is dictated in part by the architecture.

² Architectural support can greatly simplify or complicate the OS.

CMPSCI 377: Operating Systems Lecture 2, Page 4

Department of Computer Science, UMass Amherst Andrew H. Fagg

Modern Operating System Functionality

1. Concurrency: Doing many things simultaneously (I/0, processing,

multiple programs, etc.)

² Several users work at the same time as if each has a private machine

² Threads (unit of OS control) - one thread on the CPU at a time, but

many threads active concurrently

2. I/O devices: let the CPU work while a slow I/O device is working

3. Memory management: OS coordinates allocation of memory and

moving data between disk and main memory.

4. Files: OS coordinates how disk space is used to store multiple ¯les

5. Distributed systems & networks: allow a group of workstations to

work together on distributed hardware

CMPSCI 377: Operating Systems Lecture 2, Page 5

Department of Computer Science, UMass Amherst Andrew H. Fagg

Summary of Operating System Metaphors

² OS as juggler: providing the illusion of a dedicated machine with in¯nite

memory and CPU.

² OS as government: protecting users from each other, allocating

resources e±ciently and fairly, and providing secure and safe

communication.

² OS as complex system: keeping OS design and implementation as

simple as possible is the key to getting the OS to work.

² OS as history teacher: learning from past to predict the future, i.e., OS

design trade-o®s change with technology.

CMPSCI 377: Operating Systems Lecture 2, Page 6

Department of Computer Science, UMass Amherst Andrew H. Fagg

Generic Computer Architecture

CPU

System Bus

Disk

Controller

Printer Tape Drive

Controller Controller

Memory Controller

disk disk

printer

tape drive

Memory

CMPSCI 377: Operating Systems Lecture 2, Page 7

Department of Computer Science, UMass Amherst Andrew H. Fagg

Generic Computer Architecture (cont)

² CPU: the processor that performs the actual computation

² I/O devices: terminal, disks, video board, printer, etc.

² Memory: RAM containing data and programs used by the CPU

² System bus: communication medium between CPU, memory, and

peripherals

CMPSCI 377: Operating Systems Lecture 2, Page 8

Department of Computer Science, UMass Amherst Andrew H. Fagg

Architectural Features Motivated by OS Services

OS Service Hardware Support

Protection Kernel/User mode

Protected Instructions

Base and Limit Registers

Interrupts Interrupt Vectors

System calls Trap instructions and trap vectors

I/O Interrupts or Memory-Mapping

Scheduling, error recovery, billing Timer

Synchronization Atomic instructions

Virtual memory Translation look-aside bu®ers

CMPSCI 377: Operating Systems Lecture 2, Page 9

Department of Computer Science, UMass Amherst Andrew H. Fagg

Protection

Kernel mode vs. User mode: To protect the system from aberrant users

and processes, some instructions are restricted to use only by the OS. Users

may not:

² address I/O directly

² use instructions that manipulate the state of memory (page table

pointers, TLB load, etc.)

² set the mode bits that determine user or kernel mode

² disable and enable interrupts

² halt the machine

but in kernel mode, the OS can do all these things.

CMPSCI 377: Operating Systems Lecture 2, Page 10

Department of Computer Science, UMass Amherst Andrew H. Fagg

Protection (cont)

The hardware must support at least kernel and user mode.

² A status bit in a protected processor register indicates the mode.

² Protected instructions can only be executed in kernel mode.

² Multics: support for a hierarchy of kernel modes (components of the

kernel were protected from each other).

CMPSCI 377: Operating Systems Lecture 2, Page 11

Department of Computer Science, UMass Amherst Andrew H. Fagg

Crossing Protection Boundaries

System Call

Trap Handler System Service Routine

Kernel Mode

User Mode

Process

Trap to Kernel Mode

User Programs

OS Kernel

CMPSCI 377: Operating Systems Lecture 2, Page 12

Department of Computer Science, UMass Amherst Andrew H. Fagg

Crossing Protection Boundaries (cont)

System call: OS procedure that executes privileged instructions (e.g., I/O)

² Causes a trap, which vectors (jumps) to the trap handler in the OS kernel.

² The trap handler uses an ID parameter from the system call to jump to

the appropriate handler (I/O, Terminal, etc.).

² The handler saves caller's state (PC, mode bit) so it can restore control

to the user process.

² The architecture must permit the OS to verify the caller's parameters.

² The architecture must also provide a way to return to user mode when

¯nished.

CMPSCI 377: Operating Systems Lecture 2, Page 13

Department of Computer Science, UMass Amherst Andrew H. Fagg

Memory Protection

² Architecture must provide support so that the OS can:

{ protect user programs from each other, and

{ protect the OS from user programs.

² The simplest technique is to use base and limit registers.

² Base and limit registers are loaded by the OS before starting a program.

² The CPU checks each user reference (instruction and data addresses),

ensuring that it falls between the base and limit register values.

CMPSCI 377: Operating Systems Lecture 2, Page 14

Department of Computer Science, UMass Amherst Andrew H. Fagg

Memory Protection (cont)

Program B

Program C

Limit Register

Base Register

Program A

Memory

CMPSCI 377: Operating Systems Lecture 2, Page 15

Department of Computer Science, UMass Amherst Andrew H. Fagg

Traps

² Traps: special conditions detected by the architecture

{ Examples: page fault, write to a read-only page, over°ow, systems call

² On detecting a trap, the hardware:

{ Saves the state of the process (PC, stack, etc.)

{ Transfers control to appropriate trap handler (OS routine)

¤ The CPU indexes the memory-mapped trap vector with the trap

number,

¤ Jumps to the address given in the vector, and

¤ Starts to execute at that address.

¤ On completion, the OS resumes execution of the process.

CMPSCI 377: Operating Systems Lecture 2, Page 16

Department of Computer Science, UMass Amherst Andrew H. Fagg

Traps

Trap Vector:

0: 0x00080000 Illegal Address

1: 0x00100000 Memory Violation

2: 0x00100480 Illegal Instruction

3: 0x00123010 System Call

: : : : : :

² Modern OS use Virtual Memory traps for many functions: debugging,

distributed VM, garbage collection, copy-on-write, etc.

² Traps are a performance optimization. A less e±cient solution is to insert

extra instructions into the code everywhere a special condition could arise.

CMPSCI 377: Operating Systems Lecture 2, Page 17

Department of Computer Science, UMass Amherst Andrew H. Fagg

I/O Control

² Each I/O device has a little processor inside it that enables it to run

autonomously.

² CPU issues commands to I/O devices, and continues

² When the I/0 device completes the command, it issues an interrupt

² CPU stops whatever it was doing and the OS processes the I/O device's

interrupt

CMPSCI 377: Operating Systems Lecture 2, Page 18

Department of Computer Science, UMass Amherst Andrew H. Fagg

Memory-Mapped I/O

² Enables direct access to I/O controller (vs. being required to move the

I/O code and data into memory)

² PCs reserve a part of the memory and put the device manager in that

memory (e.g., all the bits for a video frame for a video controller).

² Access to the device then becomes almost as fast and convenient as

writing the data directly into memory.

² Before memory-mapped I/O: the instruction set provided speci¯c

operations for I/O. Why do we not do this very often now?

CMPSCI 377: Operating Systems Lecture 2, Page 19

Department of Computer Science, UMass Amherst Andrew H. Fagg

Interrupt based asynchronous I/O

² Device controller has its own small processor which executes

asynchronously with the main CPU.

² Device puts an interrupt signal on the bus when it is ¯nished.

² CPU takes an interrupt.

1. Save critical CPU state (hardware state),

2. Disable interrupts,

3. Save state that interrupt handler will modify (software state)

4. Invoke interrupt handler using the in-memory Interrupt Vector

5. Restore software state

6. Enable interrupts

7. Restore hardware state, and continue execution of interrupted process

CMPSCI 377: Operating Systems Lecture 2, Page 20

Department of Computer Science, UMass Amherst Andrew H. Fagg

Direct Memory Access (DMA)

² Purpose: Large I/O operations

² Processor ¯rst con¯gures the device for the transfer

² Processor then grants (or shares) control of the system bus to the device

² Device generates interrupt on completion of the transfer

² Useful for ???

CMPSCI 377: Operating Systems Lecture 2, Page 21

Department of Computer Science, UMass Amherst Andrew H. Fagg

Direct Memory Access (DMA)

Useful for ???

² Video I/O

² Audio I/O

² Disk operations

CMPSCI 377: Operating Systems Lecture 2, Page 22

Department of Computer Science, UMass Amherst Andrew H. Fagg

Timer & Atomic Instructions

Timer

² Time of Day

² Accounting and billing

² CPU protected from being hogged using timer interrupts that occur at

say every 100 microsecond.

² At each timer interrupt, the CPU chooses a new process to execute.

² At every change in process, the operating system performs a context

switch

CMPSCI 377: Operating Systems Lecture 2, Page 23

Department of Computer Science, UMass Amherst Andrew H. Fagg

Synchronization

² Interrupts interfere with executing processes.

² OS must be able to synchronize cooperating, concurrent processes.

) Architecture must provide a guarantee that short sequences of

instructions (e.g., read-modify-write) execute atomically. Two solutions:

1. Architecture mechanism to disable interrupts before sequence, execute

sequence, enable interrupts again.

2. A special instruction that executes atomically (e.g., test&set).

CMPSCI 377: Operating Systems Lecture 2, Page 24

Department of Computer Science, UMass Amherst Andrew H. Fagg

Virtual Memory

² Virtual memory allows users to run programs without loading the entire

program in memory at once.

² Instead, pieces of the program are loaded as they are needed.

² The OS must keep track of which pieces are in which parts of physical

memory and which pieces are on disk.

² In order for pieces of the program to be located and loaded without

causing a major disruption to the program, the hardware provides a

translation look-aside bu®er to speed the lookup.

CMPSCI 377: Operating Systems Lecture 2, Page 25

Department of Computer Science, UMass Amherst Andrew H. Fagg

Summary

Keep your architecture book on hand.

OS provides an interface to the architecture, but also requires some

additional functionality from the architecture.

) The OS and hardware combine to provide many useful and important

features.

CMPSCI 377: Operating Systems Lecture 2, Page 26

Department of Computer Science, UMass Amherst Andrew H. Fagg

Next Time

Wednesday:

² Read chapter 3

² Lab 0 due

CMPSCI 377: Operating Systems Lecture 2, Page 27