As Moore’s Law predicted, the data densities on chips are multiplying over time. This is allowing more and more functionality to be put on the chip. At the same time, market demand, new tools, and competitions have reduced chip development cycles to approximately a year while the time to create a derivative product has further reduced by half.

By most estimates, verification takes 60% of the total development time. Therefore finding efficient and accurate way to chip verification will significantly improve development cycles.

The sizes and complexities of new designs demand complete and faster verification. One way to reduce development time is to reuse the verification environments created in system domain, and to perform system verification early in the design cycle. The solution, currently and successfully being used to address both issues at the same time is the development of cycle-accurate or more abstract models of software algorithms using SystemC.

To address this growing demand, Thinklake Design is focused on providing design verification services based on HVLs, such as SystemC.