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Verilog FAQ      Version 09/05: September 2005


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Part 3

Tools and Services

This page lists commercially available tools and services related to Verilog. This list is not exhaustive. Reader should treat this just as a starting point and make his/her own further research and evaluations.

Simulators
Timing Diagram Designer
Simulation Results Browser
Verilog Static Checking Tools
VHDL to Verilog converters
Verilog Code Coverage Tools
Visual Verilog Tools
C to Verilog Converter 
Verilog to C/C++/SystemC Converter
Commercial source of Verilog Models  
 

Simulators
 
 
Name of the company Name of Simulator Further Information
Avanti Corporation  Polaris http://www.avanticorp.com
Cadence Design Systems, Inc. NC Verilog & Verilog-XL http://www.cadence.com
Synopsys Inc. VCS http://www.synopsys.com/
SynaptiCAD Inc.  VeriLogger Pro  http://www.syncad.com/
Fintronic USA, Inc.  FinSim http://www.fintronic.com/
InnoLogic Systems Inc. ESP Symbolic Simulator http://www.innologic-systems.com/
Mentor Graphics QuickHDL http://www.mentor.com/
Model Technology  V-System/VLOG http://www.model.com/
Dolphin Integration SMASH http://www.dolphin.fr/
Simucad Silos III http://www.simucad.com/

Timing Diagram Designer 
Timing diagrams are used to define and share design specifications among design team members. Some tools support timing diagram to RTL and test bench HDL code generation also.

The commercially available tools are
 

  1. TimingDesigner

  2. TimingDesigner Professional is an interface design tool that allows you to specify and analyze complex circuit interfaces up front in the design process. The resulting interface specification can then be used to accurately communicate your design details to other people, teams, and design tools. 
    Visit http://www.chronology.com/timingdesigner/index.html for more details.

    TimingViewerTM is a free timing diagram display and analysis tool from Chronology. More information about it is available at http://www.chronology.com/timingdesigner/tviewer.html

  3. Timing Diagrammer

  4. Timing Diagrammer Pro has everything that you expect in a timing diagram editor: a model less drawing and editing environment; delays, setups, and holds for performing timing analysis; time markers; seven graphical waveform states; virtual and group busses; clocks with formulas; as well as a variety of ways to document your work
    Visit http://www.syncad.com/ttd_main.htm for more information.


Simulation Results Browser: 

Most companies provide built-in browser bundled with simulator (sometimes from different vendor). Here is a list of companies which provide third party browsers. 
 
Name of the company Name of Browser Further Information
Design Acceleration, Inc.  Signalscan  http://www.designacc.com
SimTech VirSim http://www.simtech.com/
NOVAS Software Inc.  Debussy http://www.novas.com
Veritools Inc. Undertow VIII http://www.veritools-web.com

Verilog Static Checking Tools
Verification and Debugging time can be reduced by using Static Checking tools or so called "linting" tools. The need for such tools arises from these facts.
- Synthesis tools utilize subset of Verilog syntax. It is easier and faster to find non-synthesizable constructs in RTL code and fix them before design goes through synthesis cycle.
- Synthesis results may vary depending on coding style. Linting tools help in finding out such code to get first pass synthesis.
- Verilog is very flexible language like C. It allows syntax which will compile but may create problem in simulation and synthesis. Some examples are

  • Comparing variables with different lenghts.  if(a[1:0] == b[2:0]) .... 
  • Using blocking, nonblocking statements where they should not be used  
  • Latch Inference and many more. 
  • The commercially available Linting tools are:
    1. Nova-Verilint  from Avant! 
    2. nLint from Novas
    3. VN-Check from TransEDA


VHDL to Verilog converters
VHDL to Verilog (and Verilog to VHDL also) are the tools which take code in one format and convert them into other format. Generally they convert code module by module basis to maintain the hierarchy. 

This tools are used 

1] To reuse existing designs. 
2] To maintain both version of a design. Verilog for commercial, industrial purposes and VHDL for DoD requirements. 
3] To design, support the code for different countries like US, Europe and or Asia where preference for particular language differs. 

Commercially such tools are available from 
 
 
Name of the company Further Information
Alternate System Concepts, Inc  http://www.ascinc.com/products/vhdl2v/index.htm
Avanti Corp. http://www.avanticorp.com/product/1,1172,14,00.html
X-Tek Corporation http://www.x-tekcorp.com/Xhdl.php
FTL Systems http://www.ftlsystems.com/

Verilog Code Coverage Tools
HDLScore (Vericov) : Innoveda 
http://www.innoveda.com/products/datasheets_HTML/hdlscore.asp

VN-Cover of Verification Navigator from Transeda
http://www.transeda.com/

Covermeter from Advanced Technology Center.
http://www.covermeter.com/  It is recently bought by Synopsys.

SureCov from Verisity 
http://www.verisity.com/products/surecov.html

coverscan from Design Acceleration
http://www.designacc.com/products/coverscan/
Cadence acquired DAI.
 

Visual Verilog Tools
Visual Verilog HDL tools help design engineers in creating optimized HDL code from graphics like block diagrams, state machine diagrams, flow charts, truth tables. This increases productivity by taking understanding of design to a higher abstraction.

Some tools also convert existing code to graphics to help reuse existing Intellectual Property. Following tools are commercially available. 
 

  1. Renoir from Mentor Graphics
C to verilog Converter
C is widely used language for specification and verification of system architectures and algorithms for complex electronic systems and ICs such as digital signal processors (DSPs), and microprocessors in the computer, communications, consumer, and military markets. To implement these designs in hardware, engineers must manually translate their C code into a hardware description language (HDL). This HDL description is used to drive logic synthesis. 

Verilog to C/C++/SystemC Converter
Simulation of complex and large chip using only Verilog takes lot of time to simulate. Many companies are taking route of simulating equivalent C/C++ models of chips or part of chip with Verilog. 

C model can be equivalent but not cycle accurate. To get cycle accurate C/C++ model one can use conveters to speed up the conversion process.

Commercial source of Verilog Models

Design project require Verilog simulation models of peripherals and bus functional models for standard bus to simulate design environment for verification. Many companies are providing such models in various flavors.

- Memory models

Micron 

- Simpod Inc.www.simpod.com provides a hardware modeler called as DeskPODô that provides fast, accurate models for system design and HW/SW co-verification. DeskPOD serves as a full-functional logic simulation model, a bus-functional model, and as a platform for software development.

- Other providers which provide commercial models
http://www.synopsys.com/products/lm/modelDir.html
http://www.caesium.com/
 

Models of off-the-shelf devices from non-commerical sources:
http://vhdl.org/fmf/wwwpages/Verilog.html
 

Companies offering Verilog models of their own components:
http://www-3.ibm.com/chips/techlib/techlib.nsf/pages/main
http://www.altera.com/support/examples/verilog/verilog.html
 

Sources of Verilog models not of off-the-shelf devices:
http://www.ee.rochester.edu:8080/users/sde/research/software/verilog/hdl_dnld.html
http://www.mindspring.com/~tcoonan/newpic.html

 

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Copyright Rajesh Bawankule  1997 - 2005