Free Timing Diagram Tool
The TimingAnalyzer can be used to draw
timing diagrams of digital interfaces and check for timing problems in
digital system designs. Signals, clocks, buses, delays, constraints, states,
logic gates, counters, and shift registers are easily added from the gui.
Free VHDL to Verilog RTL translator
Vincenzo Liguori has released a VHDL to Verilog RTL translator under
GPL. Although limited, this program correctly translated his Triple DES and JPEG cores.
It is based on YACC/ C and it has been tested on Linux and Sun. You can fetch it at our download page:
Free IP Cores
Free-DES -- A DES encryption/decryption engine.
Over 363 megabytes/second in an FPGA!(VHDL)
Free-6502 -- An 8-bit micro controller that
is software compatible with the standard 6502.(VHDL)
Free-RAM -- A portable and parameterized RAM
core, including FIFO's and dual port RAM's.(VHDL)
Free-RISC8 -- An 8-bit micro controller that
is binary compatible with another popular CPU.(Verilog, plus experimental VHDL)
Free-LIB1 -- A library of NCO, DAC, and PWM
parameterized cores in VHDL, plus software to analyze the frequency spectrum
of their outputs.
Free-CORDIC -- The CORDIC (COordinate Rotation
Digital Computing) core.
Freely available IP cores like Mini-RISC
CPU/Microcontroller, compatible with the PIC 16C57 from Microchip
Free Memory Cores
European Space Agency developed their
own ERC32 which is a radiation-tolerant SPARC V7 processor developed for
space applications. Loads of information is available from this site.
Joon Lee maintains this site with free cores for 12bit
DSP core and
peripherals, 8 bit CISC processor, Self contained "single-chip" frequency
counter, SDRAM Controller etc.