Arvind Agrawal
Summary
I have more than 10 years experience in high-speed ASIC design starting
from architecture, design, implementation, verification, synthesis and
Static Timing Analysis (in Synopsys and IBM tools), helping in layout
etc. I have been actively involved in more than 5 successfully proven
and working ASICs.
Objective
Seeking full time position in ASIC design and architecture field with creative
designs and technically innovative thinking apart from good
programming skills.
Education
B.Tech in Computer Science and Engg. (Indian Institute of technology,
IIT, Delhi, 1995)
Computer Skills
HDL's known |
: Verilog, VHDL |
Scripts |
: Familiarity with Perl, Csh, Html |
Tools used |
: Synopsys Design Compiler, PrimeTime, IBM Einstimer |
Simulation Tools |
: Synopsys VCS, Verilog-NC, Virsim, SimWaves |
Professional Experience
1. Project Manager in Netlogic Microsystems, Mountain View, CA, Feb 2006 till date
2. Electronic Design Engineer Principal in Cypress Semiconductor, San Jose, CA, July 2002 to Feb 2006
3. Sr. Hardware Engineer in TeraOptic Networks,
Sunnyvale, CA, Jan. 2001 to July 2002
4. Sr. R & D Engineer in Design Reuse Group of Synopsys Inc.
Mountain View, California, USA from Nov 1999 to Jan 2001.
5. Member of Technical Staff in Chiplogic Inc.
Santa Clara, California, USA from July 1998 to Nov 1999.
6. Member of Technical Staff in Duet Technologies Pvt.
Ltd. Noida, India, July 1997 to June 1998
Project Experience
04/06 - till date: Architecture, Design, Implementation and Verification of the line rate IPS/IDS security processor NLS1000
This is the first IPS/IDS Security device at 10G in the market.
07/02 - 07/05: Architecture, Design, Implementation and Verification of the
Algorithmic Search Engine chip CYNSE50000
This is the first Network Search Engine (NSE) chip in the industry with 250 MSPS
throughput for packet forwarding using algorithms instead of CAMs. I was involved
from the start of the architecture to the completion of the manufacturing flow of
chip.
09/01 - 06/02: Design, Implementation, Synthesis and Verification of the
integrated switch fabric chip INPAQ-10
This is the integrated one chip solution for switching packets taking data
from Network Processor with speeds upto OC-192 and giving it to the Crossbar
on the ingress side and reverse on the egress side. This chip had on-chip
Quad-Serdes, 2 PLLs, SPI 4.2 de-skewing cores, PCI Target, QDR memory Interface
and CSIX-L1 protocol. This chip is 937 pin HBGA custom package in IBM SA-27E
0.15u technology with core speed of 250 MHz. My work involved
- Design, implementation, synthesis and verification of the Header Insertion,
Header Removal and CSIX-L1 Ingress and Egress, PCI Interface, Configuration
register modules for the chip (Verilog).
- Full chip synthesis in Synopsys Design Compiler
- Timing assertion scripts for the IBM Einstimer Tool to be used in backend.
02/01 - 08/01: Synthesis and Verification of the Fabric Queueing Engine chip
for Switch Fabric architecture
This project involved verification of the whole chip using Verilog testbench,
writing test cases and debugging the waveforms. This queueing and buffer
management chip takes the data segments from the Line Card Chip and sends
the frames to the crossbar for switching in the ingress side and takes the
frames from the crossbar on the egress side and transmits segments back to
the destination line card. My work included
- Analyzing and writing test cases, running and debugging for the Flow Control,
Configuration registers and Queue management modules
- Hierarchical synthesis of the complete chip at 166 MHz in LSI 0.18u g12d
technology in Synopsys Design Compiler and Primetime Static Timing Analysis.
- Also to help in the timing closure, some design modules were modified so
that they were able to meet the desired frequency.
01/01 - 06/01: Synthesis and Verification of the Fabric Port Controller
chip for Switch Fabric architecture
This project involved verification of the whole chip using Verilog testbench,
writing test cases and debugging the waveforms. This Line Card Interface takes
the packets from the network processor or traffic manager and transmits to the
queueing chip on the ingress side and vice-versa on the egress side. My work
included
- Analyzing and writing test cases, running and debugging for the Ingress
and Egress User logic and Configuration register modules
- Hierarchical synthesis of the complete chip at 166 MHz in LSI 0.18u g12d
technology in Synopsys Design Compiler and Primetime.
- Gate Level Verification was done along with Formality between RTL-gate and
gate-gate after gate level changes using Formality Tool.
11/99 - 01/01: Design, implementation, verification and synthesis of the
PCI-X bus IP core
This project involved design, implementation, verification and synthesis of
some modules (Requester and Interface modules) of the PCI-X bus architecture,
which can function both in the PCI 2.2 mode and PCI-X 1.0 mode. It included
writing the design and test document and verification at the module level
and at the chip level. (Verilog)
07/98 - 06/99: Design and RTL implementation of Memory Tester ASIC:
This project for Teradyne Inc. involved design and development of RTL code
for one of the ASICs to be used in the memory tester Board of Teradyne.
My work involved Verilog RTL code development, Boundary Scan (JTAG) insertion,
Synthesis and Timing Analysis, Power calculation and analysis, pinout generation,
Gate level verification with the pre-layout SDF file, helping the fab. in layout,
Test vector Generation for the Post fabrication testing. This was a complicated
design of 160K gates and 130K RAM running at 50 MHz in 0.35 ( technology. This
was a heavily pipeline architecture with software programming capability. Later
I helped in software environment setup for the software verification which
included hooking up of additional RTL code of other Asics on the board. (Verilog,
Synopsys Design Compiler, Verilog-NC, Simwaves and some Fab. tools)
07/99 - 11/99: Verification of the M13 Multiplexer-Demultiplexer
This project for Infineon involved verification of the M13
multiplexer/Demultiplexer from the T1.107, G.747 and other standards.
The work involved understanding the standards required and making the
test cases from the application point of view and checking that the
device is compliant to the respective standards. (VHDL)
06/99 - 09/99: Top level Architectural design of the MAC to SONET
controller, Mapper and Framer
This project still in the initial design phase involves reading, top level
architectural design and understanding different issues involved with
Ethernet MAC to SONET converter using the HDLC frame structure, VT level
mapper/demapper and also supporting direct DS1 inputs to convert them to
the SONET frames.
08/97 - 05/98: Design of Bus Interface Models for Hardware Software
Co-verification tool
This project for Mentor Graphics involves cosimulation of the hardware with
the virtual model for some embedded processors. Bus Interface Model (BIM)
were developed for some particular MIPS R4000 processors which were available
as shared library in Hardware Software Co-verification (Seamless CVE) environment.
This will be used for Asics and processor development and simulations.
(C and VHDL used)
09/97 - 11/97: Verilog designs for testing MIPS processor
Test designs were developed in Verilog for complex Toshiba's RISC processor
with many peripherals, to verify the Bus Interface Model developed
in Co-verification environment. This behavioral model verified and simulated
the working of the RISC processor. (Verilog and VHDL used)
05/94 - 07/94: Device Driver for the Termport Card
Design and software implementation of the device driver for the termport
card for multiple, simultaneous, serial/parallel I/O using MS-DOS interrupt
Int14h in C and Assembly language. This is used in the Termport Printed
Circuit Board (PCB). Also complete library utilities were developed for
the front end applications for Infocom Digital Systems Pvt. Ltd. New Delhi.