Experiments on

Computer Systems Architecture

Experiment #1

Register Set

Description

    Part of the microprocessor does the basic operation in the CPU. After implementing so, it shows the output in a certain set of         registers available in it.

Objectives

1.      To be able to understand the operations of different register and data processor of a basic CISE processor.

2.      To be able to design a VHDL that will perform the different operations of registers and ALU

3.      To be able to simulate a VHDL code of design using the MAX+PLUS tools.

Theoretical Framework

            The computer unit is made up of three major components, the arithmetic/logic unit (CU), and memory. The ALU and CU together are known as the Central Processing unit or the CPU. The I/O or input/output interface corresponds in function roughly to the input and output.  The arithmetic/logic unit is the component of the CPU where data held temporarily and whore calculations take place.

            The control unit interprets and controls the execution of instruction. It does so by following a sequence of actions corresponds to the fetch- execute cycle. Most of this cycle or actions are movements of data or address from one part of the CPU to another.

            The control unit determines the particular instructions to be executed by reading the contents of a program counter (PC), which is part of CU. The PC contains addresses of the current instructions or the next instruction to be executed. Normally, instructions are executed sequentially. The sequence of instructions is modified by executing instructions that change the content of program counter.    

 The Concept of Registers

             A register is a single permanent storage location w/in the CPU used for a particular, defined purpose. It is used to hold a binary value temporarily for storage, for manipulation, and/or for simple calculations.

            Registers are differ from memory in that they are not addressed as a memory location would be, but instead are manipulated directly by the control unit during the executions of instructions.

            Register are used in many ways in a computer. Depending on the particular used of registers, it may hold data being manipulated or processed, an instruction being executed, a memory or I/O addressed, or even special binary codes used for some other purpose, such as codes that keep track of the status of the computer or the conditions of calculations that may be used for conditional branch instructions.

            In the CPU, the equivalent to the calculator is known as ACCUMULATOR. There are several accumulators in a real CPU. The general purpose register or user visible registers. It indicates that they may be accessed by the instructions is used program. In most computers accumulators are considered them as a separated register unit.

            Accumulators hold the data that are used for arithmetic operations as well as the results. It also transfers data between different memory locations and between I/O and memory.

            Program counter- it holds the address of the current instruction being   executed.

            Instruction register- it holds the actual instruction being executed currently by the computer.

Memory address register (MAR) – holds the address of the memory location that currently being accessed.

Memory data register (MOR) – holds a data value that being stored to or retrieved from memory location currently addressed by the memory address register.

The control unit will also contain several that register, sometimes known as FLAGS, that are used to allow the computer to keep track of special conditions such are arithmetic carry overflow, power failure and internal error.

            In addition, typical CPU will contains an I/O interface that will handle input and output data as it posses between the CPU and various input and output devices.

            Most instructions are executed by the different sequenced movement of the data between the different register in ALU and CU.

            Most registers support three primary types of operations.

1.      Registers can be loaded w/ values from other locations, in particular from other register or rather memory locations. These operations destroy the previous value stored in the register. 

2.      Data from another location can be loaded or added to a subtracted from the value previously stored in the register, leaving the sum or difference to the register.

3.      Data in the register can be shifted or rotated right or left by one or more bits.

Conceptual Framework

            In this experiment, we are to design a system that will perform different operations of registers and arithmetic logic unit (ALU), namely (1) ADD (2) ADC (3) SUB; CMP) (4) SUBB; Subtract w/ borrow (5) AND; TEST (6) OR (7) XOR (8) NOT (9) SHL (10) SHR.  These operations are classified into three (3) kinds, the mathematic operations, logic operations and shift operations, these types are to be chosen eventually by using a multiplexer.

            In order to implement those operations, different items are necessary to be incorporated, in this case, (3) register are needed, one of which performs the load operations, second register performs the increment, decrement and load operations and lastly, the third one performs the load increment and clear operations.

            To be able to come up with those registers, the following VHDL code presented.

--reg-a. vhd

       library ieee ;

      use ieee. std_logic_1164.all

      use ieee. std_logic_insigned.all

       entity reg- a is

      generic (size: integer:=8);

      port ( clk, id_a : in std_logic ;

                  in_bus : in std_logic_vector (size –i downto o));

      end reg_a;

 architecture a of reg_a is

begin (clk)

begin

if clk’ event and clk= ‘i’ then

if id-a = ‘I’ then

reg a<= in_bus;

else

reg a <= “00000000” ;

 end if ;

end if ;

 end process;

--- reg_b. vhd

 library. ieee;

use ieee. std _logic_1164. all

use ieee. std_logic unsigned. All

 entity reg_b is

generic (size : integer : = 8)

port (clk, id-b, inc_b, dec_b; in std_logic;)

      in_bus : in std _logic_ vector (7 down to 1);

regb: buffer std_logic_vector (size –I downto));

end reg-b;

architecture a of reg-b is

begin(clk)

begin process (clk, inc _b, dec-6)

 if load _b = ‘i’ inc_a = ‘i’  and

      dec _ b = ‘o’ then

out_bus <= in_bus + i ;

else if load _b = ‘i’ and dec – b = ‘i’

      and inc_b = ‘o’ then

out_ bus <= in_bus-i ;

 end if ;

and if ;

end process ;

end a ;

-- reg_c.vhd

            library ieee ;

      use ieee. std_logic_1164.all

      use ieee. std_logic_insigned.all

 entity reg_c is

generic (size: integer := 8);

port ( clk, ld_c, inc_c, clr: in std_logic;)

          in_bus: in std_logic_vector (7 downto 1);

          regc: buffer std_logic_vector ( size -1 downto 0));

 end reg_c;

 architecture a of reg_c is

 begin

process ( clk, inc_c, clr)

 begin

 if clk’event and clk = ‘1’ then

if ld_c= ‘1’ and inc_c= ‘1’ and clr= ‘0’ then

reg_c <= in_ out1+1;

 elsif ld_c = ‘1’ and clr= ‘0’ then

reg_c <= “00000000”;

end if ;

end if;

end process;

end a;

Moreover, after implementing these registers, two multiplexers will then be necessary. The VHDL code presented below are the design of multiplexer 2-1 and multiplexer 8-1 respectivel.

--- mux_2.vhd

 library ieee ;

use ieee. std_logic_1164.all

entity mux_2 is

generic ( size: integer := 8);

port ( A,B : in std_logic_vector (size-1 downto 0);

          S: in std_logic;

          Output: out std_logic_vector (size-1 downto 0));

End mux2;

Architecture mux2 of mux_2 is

Begin

Process(s)

Begin

      Case s is

When ‘0’ => output <= A;

When ‘1’ => output <= B;

When others => output <= “0”;

End case;

End process;

End mux_2;

--- mux_8.vhd

      library ieee ;

      use ieee. std_logic_1164.all

 entity mux_8 is

port (A,B,C,D,E,F,G,H is std_logic_vector (7 downto 0);

       regb_sel: in std_logic_vector (2 downto 0);

       regb_out; out std_logic_vector (2 downto 0));

 end mux_8;

architecture mux8 of mux_8 is

begin

process (regb_sel)

begin

            case regb_sel is

when   “000” => reg_out <= A;

            “001” => reg_out <= B;

            “010” => reg_out <= C;

            “011” => reg_out <= D;

            “100” => reg_out <= E;

            “101” => reg_out <= F;

            “110” => reg_out <= G;

            “111” => reg_out <= H;

when others   => ragout   <= “00000000”;

end case;

end process;

end mux_8;

            After the implementation of the above mentioned sub-component an arithmetic logic unit is necessary. Agter finishing ALU incorporation of the aforementioned are the only way to come up with the whole

            The binary inputs to be used referred by the multiplexer corresponds to different operations, as mentioned in the earlier part of the conceptual framework. The following binary codes their corresponding operation and mnemonic codes are presented below.

             The above mentioned operations are the ones to be performed in ALU. In the ALU, two opcodes are given, the multiplexer chooses operations to implement, ALU on the other hand will be the one to perform the said operations by the mux. One of the inputs is the carry (cy) for it will be taken into consideration in some of the operations given. To be able to have a clear understanding

  About the ALU the logic diagram is presented below

ALU.vhd

            library ieee ;

      use ieee. std_logic_1164.all;

      use ieee. std_logic_insigned.all;                

      use ieee. std_logic_arith.all;

 entity alu is

 port ( OP1, OP2: in std_logic_vector (7 downto 0);

            opcode: in std_logic_vector (3 downto 0);

            Ci: in std_logic;

            Alu_out: out std_logic_vector (7 downto 0);

Cy, s, z: out std_logic);

 Alu end;

 Architecture a of alu is

Signal temp: std_logic_vector (8 downto 0);

 Begin

 Case opcode (3 downto 0) is

             When “0100” => temp <= OP1+OP2;

            When “0101” => temp <= OP1+OP2+Ci;

            When “0110” => temp <= OP1+notOP2+1;

            When “0111” => temp <= (OP1+notOP2+1)-Ci;

            When “1000” => temp <= (‘0’ & OP1) AND (‘0’ & OP2)

            When “1001” => temp <= (‘0’ & OP1) OR (‘0’ & OP2)

            When “1010” => temp <= (‘0’ & OP1) XOR (‘0’ & OP2)

            When “1011” => temp <= not(‘0’ & OP1)

            When “1100” => temp <= (OP1(0)&Ci) & OP1 (7 downto 1);

            When “1101” => temp <= OP1 (7 downto 1) & Ci ;     

            When others   => temp <= “00000000”

 End case;

 Alu_out <= temp (7 downto 0);

             If temp = “00000000 then 2 <= ‘1’;             

                        Else z <= ‘0’;

                                    End if;

 If opcode = “011” then

            S<= temp(7);

 If temp (7)= ‘1’ then alu_out <= not ( temp(7 downto 0)) +1;

 End if;

Cy <= ‘1’;

End if;

Experimental Circuit Setup

 Data and Results/Tables

 Materials

 -         Windows based personal computer

-         Altera Max+Plus II

Procedures

Register A

1. construct the VHDL code for the register model register a is an 8 bit register with a load function. Save the constructed vhdl code

2. compile the constructed vhdl code

3. create a new waveform editor file. Set all the nodes from the SNF file created during compilation input into the waveform editor file

4. set a pulse signal to the clock input of the register. The pulse signal is 20MHz.

5. set an input values with 10MHz pulse signal for the register. Save and simulate.

6. copy the output waveform in the space provided in data and results.

7. verify the output of the simulated data corresponds to that the behavior of the register complies with that what is expected from it in the conceptual framework.

Register B

1. Design a vhdl code that will perform the function set for register b. register b is an 8 bit register with load, increment and decrement function.

2. save the source code and set the program to current file

3. compile the vhdl code

4. Open the waveform editor and be able to set all the SNF nodes into the waveform editor file.

5. set the particular values to be utilized for each of the input lines. 20MHz pulse signal for clock input and 10MHz pulse signal for the inputs

6. save the SNF file produced.

7. simulate the completed SNF files

8. be able to copy the simulation diagram in the data and results sheet.

9. verify the results obtained from the expected results stated in the conceptual framework.

Register C

1. design a vhdl code that will perform the function set for register c. register c is an 8 bit register with load, increment and clear function

2. save the source code and set the program to current file

3. compile the vhdl code

4. open the waveform editor and be able to set all the node into the waveform editor file

5. set the particular values to be utilized for each of the input lines. 20MHz pulse sigbal for clock input and 10MHz pulse signal for the inputs

6. save the SNF file produced

7. simulate the completed SNF file.

8. be able to copy the simulation diagram in the data and results sheet

9. verify the results obtained from the expected results stated in the conceptual framework.

 Arithmetic Logic Unit (ALU)

1. construct a vhdl code for the register model of an 8 bit ALU. The function of ALU selected by F[3..0] are the following

2. save the source code and set program to current file

3. compile the vhdl code

4. open the waveform editor and be able to set all the SNF nodes into the waveform editor file

5. set the particular values to be utilized for each of the input lines

6. save the SNF file produced

7. simulate the completed SNF file

8. be able to copy the simulation diagram in the data and results sheet

9. verify the results obtained from the expected results stated in the conceptual framework

 Analysis:

For us to have a total structure that will implement the function of a data processor we need different kinds of registers for us to store information temporarily and it’s  by then evaluated inside the  whole processor but first, must go through such types of registers.

         There are three registers that we created, one of it was a register that perform different operation namely load, another register that performs increment and decrement operation and finally a third register that perform operations such as load, clear and increment.

There are three major functions needed to perform data processing. One is that the register must recognize different data that are being loaded inside it, secondly the register must have the ability to all the operation needed to process the data. Operation such as increment, decrement, load etc., lastly the system must be capable of clearing the data that has been previously evaluated. In the 3 registers that we made our group can say that the 3 registers that we made are capable of doing these 3 vital functions proficiently.

 Conclusion:

The data processor is made up of the processor part and the outputting part. On the left hand is the processor part, it does the validation to the data that is being given by the client. And on the right hand is a thing that is capable of outputting the data after its evaluation and can be regarded as the outputting part of the system.

The processor part of the system comprises of registers and ALU. The earlier is then composed of 3 registers that are capable of reading the fetch data being fed into the system. Incrementing, decrementing each data and clearing the data from the system is basically the function of a data processor the said function must be present for the data processor to function efficiently

The Arithmetic Logic Unit or ALU is a part that is created to handle such as mathematical, logic and shift operations inside the data processor. Math operations such add, add with carry, subtract, subtract with borrow; logic operations like logic and, or etc. and shift operations like shift left and shift right, the ALU has to input and a single output.

These ALU and registers basically can be considered as vital parts on creating an operational data processor yes with the help of VHDL programming these “self-made” data processor can be a certainty.