EXPERIMENT #1: DATA PROCESSOR / REGISTER SETS

Comp421L Computer System Architecture Laboratory

TEAM 6

4 CoE A

Members:

Mark AGANON

Jeffrey CARREON

Manuel CASTILLO

EXPERIMENT #1: DATA PROCESSOR / REGISTER SETS

OBJECTIVES:

Design the data processing/ register transfer operation in a simple CISC.
Synthesize the register transfer design through VHDL code.

DESCRIPTION:

The data processor of the microcomputer is held responsible for the manipulation of data and stores it to one of the available register. Specific micro-operations is also done on the data.

THEORETICAL FRAMEWORK:

A computer unit is made up of three major components namely the data processor, control unit and memory. Sometimes it may also contain I/O devices. The data processor and control unit that composes the CPU are held responsible for the execution of instructions. In the process, data processing occurs.

The data processor can be simplified into an execution unit and bus interface unit. The ALU that is in the EU is the one responsible for the operation performed with the data stored in registers. On the other hand, the bus interface unit is a collection of register wherein data is stored.

Registers is a collection of flip-flops with added combinational gates that perform data processing tasks; the flip-flops act as binary storage cells and gates determine the new or transformed data to be transferred into the flip-flops. Registers are useful for storing and manipulating binary information.

In a simple CISC system, the common registers used are the PC, MDR, MAR, SP, IR. The PC, which is part of the control unit contains the address of the current instruction to be executed. The contents of which is necessary for the control unit to determine the particular instruction to be executed. The instruction register holds the actual instruction being executed currently by the computer. The memory address register holds the address of a memory location while the memory data register hold a data value that is being stored to or retrieved from the memory location currently addressed by the memory address register. Sometimes it is called memory buffer.

CONCEPTUAL FRAMEWORK:

In the synthesis of the design, we divided the whole system into subsystems. Each subsystem correspond to a set of function to be performed. The subsystems is then connected to each other to perform the desired operation. The subsystem includes reg_a, reg_b, reg_c, ALU, multiplexers, flag circuit, LPM_RAM and LPM_ROM.

The reg_a register is a register that is capable of loading data or simply hold data. The data is obtained from an 8-bit data bus and is stored in the register upon the event of a clock pulse. This category of register includes the MAR, MBR and the IR.

--reg_a VHDL code

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity rega is

generic (size: integer := 8);

port ( clk : in std_logic;

load_a : in std_logic;

in_bus : in std_logic_vector (size-1 downto 0);

out_rega : buffer std_logic_vector (size-1 downto 0));

end rega;

architecture rega of rega is

begin

process (clk)

begin

if(clk'event and clk = '1') then

if load_a = '1' then out_rega <= in_bus;

end if;

end process;

end rega;

The reg_b category is a register that is capable of loading data from the data bus, increment the data and decrement the data. This category of register includes the accumulator, memory, and the stack pointer.

--reg_b VHDL code

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity regb is

generic (size: integer := 8);

port ( clk : in std_logic;

load_b : in std_logic;

inc_b : in std_logic;

dec_b : in std_logic;

in_bus : in std_logic_vector (size-1 downto 0);

out_regb : buffer std_logic_vector (size-1 downto 0));

end regb;

architecture regb of regb is

begin

process (clk)

begin

if(clk'event and clk = '1') then

if load_b = '1' then out_regb <= in_bus;

end if;

if inc_b = '1' then out_regb <= in_bus + 1;

end if;

if dec_b = '1' then out_regb <= in_bus - 1;

end if;

end process;

end regb;

The reg_c category is a register that performs load, increment and clear. This category includes the PC.

--reg_c VHDL code

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity regc is

generic (size: integer := 8);

port ( clk : in std_logic;

load_c : in std_logic;

inc_c : in std_logic;

clr_c : in std_logic;

in_bus : in std_logic_vector (size-1 downto 0);

out_regc : buffer std_logic_vector (size-1 downto 0));

end regc;

architecture regc of regc is

begin

process (clk)

begin

if(clk'event and clk = '1') then

if load_c = '1' then out_regc <= in_bus;

elsif inc_c = '1' then out_regc <= in_bus + 1;

elsif clr_c = '1' then out_regc <= "00000000";

end if;

end process;

end regc;

The ALU is the one responsible for the operation done into the data. It is composed of 3

sets of operations. These are as follows:

Arithmetic operation: it includes add, add with carry, subtract, and subtract with borrow.
Logic operation: it includes OR, AND, EXOR and NOT.
Shift operation: it includes shift left and shift right.

The function table for the ALU is given below:

F3	F2	F1	F0	Operation	Mnemonic
0	1	0	0	OP1 + OP2	ADD
0	1	0	1	OP1+OP2 +Cin	ADC
0	1	1	0	OP1- OP2	SUB; CMD
0	1	1	1	OP1- OP2- Cin	SUBB
1	0	0	0	OP1 AND OP2	AND
1	0	0	1	OP1 OR OP2	OR
1	0	1	0	OP1 XOR OP2	XOR
1	0	1	1	NOT (OP1)	NOT
1	1	0	0	SHL (OP1)	SHL
1	1	0	1	SHR (OP1)	SHR

--Arithmetic Logic Unit (ALU) VHDL Code

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity alu is

generic (size: integer:=8);

port( clk :in std_logic;

Op1,Op2 :in std_logic_vector(7 downto 0);

sel :in std_logic_vector (3 downto 0);

Ci :in std_logic;

Cy :out std_logic;

Alu_Out :out std_logic_vector (7 downto 0));

end alu;

architecture alu of alu is

signal result: std_logic_vector (8 downto 0);

begin

process(clk,sel)

begin

wait until(clk'event and clk='1');

case sel is

when "0100" => result <= Op1 + Op2; --add

when "0101" => result <= Op1 + Op2 + Ci; --adc

when "0110" => result <= Op1 - Op2; --sub

when "0111" => result <= Op1 - Op2 - Ci; --subb

when "1000" => result <= ('0' & Op1) and ('0' & Op2); --and

when "1001" => result <= ('0' & Op1) or ('0' & Op2); --or

when "1010" => result <= ('0' & Op1) xor ('0' & Op2); --xor

When "1011" => result <= ('0' & not(Op1)); --not

when "1100" => result <= Op1 (7 downto 0) & Ci; --shl

when "1101" => result <= (Op1(0) & Ci) & Op1(7 downto 1); --shr

when others => result <= '0' & Op1;

end case;

alu_out <= result(7 downto 0);

Cy <= result(8);

end process;

end alu;

MATERIALS USED:

Altera Max+Plus II

Personal Computer, Windows based

PROCEDURES:

A.) Register A

1. Create a VHDL code of an 8-bit register of category Register A capable of load operation.

2. Compile the VHDL code.

3. In a new waveform editor window, input all the nodes of Register A from the SNF.

4. Provide a 20MHz clock to the register’s clock input.

5. Edit the waveform of all input signals as shown in the Table for Register A of the Data and Result part of the experiment.

6. Save and simulate the waveform editor file.

7. Record the results obtained in the corresponding table in the Data and Result part.

8. Verify the output waveform in correspond to the input data. Observe the behavior of the register when its load signal is set to logic ‘1’.

B.) Register B

1. Create a VHDL code of an 8-bit register of category Register B capable of load, increment and decrement functions.

2. Compile the VHDL code.

3. In a new waveform editor window, input all the nodes of Register A from the SNF.

4. Provide a 20MHz clock to the register’s clock input.

5. Edit the waveform of all input signals as shown in the Table for Register A of the Data and Result part of the experiment.

6. Save and simulate the waveform editor file.

7. Record the results obtained in the corresponding table in the Data and Result part.

8. Verify the output waveform in correspond to the input data.

C.) Register C

1. Create a VHDL code of an 8-bit register of category Register C capable of load, increment and clear functions.

2. Compile the VHDL code.

3. In a new waveform editor window, input all the nodes of Register A from the SNF.

4. Provide a 20MHz clock to the register’s clock input.

5. Edit the waveform of all input signals as shown in the Table for Register A of the Data and Result part of the experiment.

6. Save and simulate the waveform editor file.

7. Record the results obtained in the corresponding table in the Data and Result part.

8. Verify the output waveform in correspond to the input data.

D.) ALU

1. Create a VHDL code for an 8-bit ALU. The ALU can perform various operation selected by F[3..0] as stated in the conceptual framework.

2. Compile the VHDL code.

3. In a new waveform editor window, input all the input nodes of the ALU from the SNF.

4. Provide the input values as shown in the table for ALU in the Data and Result part.

5. Provide a 20MHz clock to the ALU’s clock input.

6. Provide a Cin input.

7. Set the 4bit select input of the ALU that correspond to desired operation.

8. Record the results obtained in the corresponding table of the Data and Result part.

9. Verify the results if the currently set operation.

10. Repeat steps 7-4 for each operation stated in the conceptual framework.

DATA AND RESULTS:

Reg_a

Clk	load_a	in_bus	out_rega
0	1	01	00
1	1	01	01
0	0	02	01
1	0	02	01
0	1	03	01
1	1	03	03
0	0	04	03
1	0	04	03

Reg_b

Clk	load_b	inc_b	dec_b	in_bus	out_regb
0	1	0	0	00
1	1	0	0	00	00
0	0	1	0	02	00
1	0	1	0	02	01
0	1	0	0	04	01
1	1	0	0	04	04
0	0	0	1	06	04
1	0	0	1	06	03
0	0	0	0	08	03

Reg_c

Clk	load_b	inc_b	clr_b	in_bus	out_regb
1	1	0	0	00	00
0	1	0	0	00	00
1	0	1	0	05	01
0	0	1	0	05	01
1	1	0	0	05	05
0	1	0	0	05	05
1	0	0	1	10	00
0	0	0	1	10	00

ALU

Clk	OP1	OP2	Cin	F	Alu_out
0	07	01	1	0100
1	07	01	1	0100	08
0	07	01	1	0101	08
1	07	01	1	0101	09
0	08	02	1	0110	09
1	08	02	1	0110	06
0	08	02	1	0111	06
1	08	02	1	0111	05
0	09	03	1	1000	05
1	09	03	1	1000	01
0	09	03	1	1001	01
1	09	03	1	1001	0B
0	0A	04	1	1010	0B
1	0A	04	1	1010	0E
0	0A	04	1	1011	0E
1	0A	04	1	1011	F5
0	0B	05	1	1100	F5
1	0B	05	1	1100	17
0	0B	05	1	1101	17
1	0B	05	1	1101	42

ANALYSIS:

Based on the data and results gathered, the characteristic of each register were shown. This was specifically seen in the timing waveforms that were generated when the register designs were simulated.

As seen in the timing diagram of Register A, the 8-bit data in the bus (in_bus) was loaded in the register (Reg_a) whenever the load_a signal went high upon the positive edge of the clock. Through the clock was high, the 8-bit data in the bus wasn’t stored in the register when its load_a signal was low or simply, had a logical value of ‘0’. Also, when the clk signal was low though load_a signal had a logical value of ‘1’, the 8-bit data wasn’t still loaded into the register. Same thing happens when both, the clk signal and load_a signal are low. Thus, clk signal and load_a signal must both be high or logically ‘1’ in order for the data to be loaded into Register A. Clearly, this explains the load function which Register A exhibits.

Register B whose function includes loading data from the data bus, incrementing the data and decrementing the data was clearly explained through its timing waveform. Like Register A, Register B is also capable of the load function which works exactly the same as with Register A. Both the clk signal and the load signal (load_b) must be high in order for the 8-bit data from the bus to be loaded into the register. The increment function of Register B is capable of incrementing the 8-bit data that was previously stored in the register by’1’. This happens whenever both the clk signal and the inc_b signal are high. If one of these signal goes low, the data in the register and not in the bus remain the same. This is clearly shown in the table for reg_b. The 8-bit data ‘00’ that was previously loaded into the register remained unchanged since clk signal is low, regardless of inc_b signal being high. The 8-bit data ‘00’ was neither incremented. Thus, increment function of Register B increments the data in the register that was previously loaded into it and that the 8-bit data in the bus (in_bus) when both clk signal and inc_b signal are high. Same theory of operation is true for the register and not the data in the bus while the increment function increments the data in the register. As shown in the table of reg_b, the data ‘04’ in the register that was previously loaded was decremented by ‘1’ since both the clock signal and dec_b signal are high. Also, notice that the 8-bit data ‘06’ that was present in the bus was not the one decremented. This clearly shows that the data must first be loaded in to the register before it can be decremented or incremented.

Register C is also capable of load function like the two registers. Its behavior is similar to the theory of operation of load function of both Register A and Register B. The clk signal and the load signal (load_c) must be both high in order for the 8-bit data in the bus to be loaded in the register. As seen in the table, the 8-bit data ‘05’ that is present in the bus was loaded into the register only when the clk signal became high as well as the load_c signal. It was not loaded into the register when one of these signals was low or both were low. Also, same principle of operation is true for the increment function of Register C like that of Register B. The 8-bit data in the register that was previously loaded is incremented when both the clk signal and inc_c signal became high. Also, the data in the register was the one incremented and not the data present in the bus. As seen in the table, the 8-bit data ‘00’ that was previously loaded was incremented when clk and inc-c signal became high though the 8-bit data ‘05’ was present in the bus. It was the data ‘00’ that was incremented that changed to ‘01’ and became the new data in the register. In addition to these functions, Register C also has a clear function. The clear function of Register C simply clears the data in the register when both clk and clr_c signal are low. In the process, the data present in the register is replaced by the 8-bit data ‘00’. As seen in the table for reg_c, the 8-bit data ‘00’ was loaded into the register replacing its previous data, ‘05’, when both clk and clr_c signal became high . The data in the register is therefore cleared.

Also, only one function of the register is implemented at a time. This is true for both Register B and Register C. They cannot perform 2 or more of its function at the same time. As seen in the table, only one function signal becomes high at a certain time besides the clk, thus only one operation is performed.

With this, the register implementation is said to be synchronous since it depends on clock pulses before it does the register function when on of its signal goes high.

The ALU that is responsible for the operation done on the 8-bit data is implemented by supplying the two operands, the carry-in flag and the function select that determines which of the arithmetic, logic or shift operation to be performed. Based on the table for the ALLL, when F= ‘0100’, the code performs add operatio on the two operands, namely OP1 and OP22 upon the even of the clock pulse (clk = ‘1’). In this operation, the ALU outputs, the 8-bit sum and the one bit carry flag. Notice that the carry-in flag is not used since the operation selected is simply addition without carry. In order to perform subtract with borrow, F is set to ‘0111’ as seen in the table. In the process, OP2 is subtracted from OP1 and the carry in flag is then subtracted. The operations NOT, SHL and SHR are being done only on the first operand (OP1). OP2 is not used when these operations are being set through F signal. Like the registers, the ALU implementation is also considered synchronous since it waits for the clock to be high before it execute the desired operation. Also, only one operation is done at a time. This is clearly shown by the timing waveform of the ALU or either by the table of the ALU.

It is also noticed in the waveform that whenever clock is low, the operation set is not performed even though it is a new one. The operands are not used and the output remained the same as the result of the previous operation done. As seen in the table, the output remained ‘08’ although a new operation is set since the clk is low.

CONCLUSION:

Data processing in a microcomputer is done inside the central processing unit specifically through bus interface unit (BIU) and the execution unit (EU). The BIU is the one responsible for the storage of binary information used and provide data path for the said data. On the other hand, specific micro-operations is done on the datra by the EU. It is the one responsible for the manipulation of data available in the BIU.

The bus interface unit is composed of registers which is a collection of flip-flops with added combination gates that perform data processing tasks namely storing and manipulating binary information., The registers present in the BIU are the PC, MDR, SP, IT and MAR. The PC, which is part of the control unit, contains the address of the current instruction to be executed. The IR holds the actual instruction being executed currently by the computer. The MAR is the one that holds the address of a memory location while the MBR hold a data value that is being stored to or retrieved from the memory location currently addressed by the memory address register.

In the design implementation, these registers are classified into three categories according to the functions they are capable of. These registers are reg_a, reg_b and reg_c. Reg_a is capable of loading data obtained from an 8-bit data bus. The load function is done whenever the clk signal and the load signal are both logical ‘1’ or high. The registers classified into this category are the MAR, MBR and the IR. Reg_b, on the other hand, is capable of load, increment and decrement function. The load function works like the load function of reg_a. The increment function increments the 8-bit data stored in the register whenever the clk signal and the increment signal become high. This function does not increment the data present in the bus but rather the data in the register. Thus, it must loaded first into the register before it can be incremented. The decrement function of reg_b decrement by ‘1’ the data loaded into the register whenever the clk signal and decrement signal are both high. The registers included in this category are the accumulator of the EU, the M (memory register) and the SP. Reg_c is capable of load, increment and clear functions. Its load and increment function works like the load and increment function of reg_b. They employ the same principle. The clear function of reg_c simply clears the content of the register by replacing it with a value of ‘00’ whenever both the clk and clear signal are high. The register classified into this category is the PC.

The execution unit that manipulates the data stored in the BIU mainly consists of the ALU and the accumulator. Also, this unit holds the operation to be done on the data. The accumulator is a register that holds all arithmetic and logical operation results. On the other hand, the ALU is the one responsible on the operation to be done on the data. These operations include arithmetic, logic and shift operations.

The control signals for the register functions are one-bit signal each that is either high or low. For the ALU, a 4-bit select is used to choose the desired operation to perform depending on the combination.