OBJETIVES:

 

Ø        To implement the control unit of a basic 8-bit CISC microprocessor capable of executing the given set of instructions.

 

Ø        To design the control unit that will generate the necessary control signals dependent on the current instruction, T-state and timing sequence.

 

Ø        To synthesize the design using VHDL.

THEORETICAL FRAMEWORK: 

The CPU, which can be considered the heart of the computing system, includes three main components: the control unit (CU), one or more arithmetic logic units (ALU) and various registers. The control unit determines the order in which instructions should be executed and controls the retrieval of the proper operands. It interprets the instructions of the machine. The execution of each instruction is determined by a sequence of control signals produced by the control unit. In other words, the control unit governs the flow of information through the system by issuing control signals to different components. Each operation caused by a control signal is called a microoperation.

The control unit is the most important part of an automatic digital computer. It is, in fact, the part that makes it automatic. The main function of the control unit is to decode the order digits of an instruction word, thereby generating the necessary sequence of control waveforms (micro-orders) to allow the instruction to be executed during the execute cycle. The other basic requirement is to provide the signals which allow the instructions to be read down in sequence form the main store, that is, the read cycle operations. Thus the control unit must generate as many different sequences of gating or switching waveforms (micro-programs) as the number of different arithmetic, logical or transfer operations that computer is required to perform.

In general, there are two main approaches for the implementation of a control unit, namely the hardwired circuit and the microprogram design. The hardwired approach to implementing a control unit is most easily represented as a sequential circuit based on different states in a machine; it issues a series of control signals at each state to govern the computers operation. As an example, consider the design of a hardwired circuit for the load instruction of the simple microcomputer mentioned previously. This instruction has the format: LOAD Rd, address. As such, it would load the contents of a memory word into register Rd.

One main drawback is a later change in the control unit requires the change of the whole circuit. The rationale for considering this a drawback is that a complete instruction set is usually not definable at the time that a processor is being designed, and a good design must allow certain operations, defined by some later user, to be executed at a very high speed.

In order to solve the inflexibility problem with a hardwired approach, a technique called microprogramming was invented. A microprogram design resembles a computer within a computer it contains a special memory from which it fetches and executes control information, in much the same manner as the CPU fetches and executes instructions form the main memory. In this design, each machine instruction translates into a sequence of microinstructions that triggers the control signal of the machines’ resources; these signals initiate fundamental computer operations.

A typical hardwired control unit is composed of instruction decoder, the sequence generator and the control matrix. The instruction decoder is the one that decodes the instruction from the instruction register. On the otherhand, the sequence generator determines the flow or sequence of the execution of each instruction. The control matrix composed of components that generates control signals as a function of the instruction currently being executed, the status flag and the step generator/ sequence generator. At reset, the sequence generator starts to count and 00H is loaded to the program counter. 

CONCEPTUAL FRAMEWORK:

 

     The control unit is a critical subsystem central processing unit for it the one held responsible for the generation of control signals to perform a given instruction. In its design, it is necessary to determine the instruction set and its corresponding binary code. In addition to this, the mnemonic codes for each instruction must also be established since it designates the register transfer operations and all other internal operations in the execution of the instruction.

 

Below is the table of the instruction sets to be implemented and their corresponding register transfer language, T-states and Boolean expression.

 

 

In the synthesis of the design, we divided the whole system into subsystems.  Each subsystem corresponds to a set of function to be performed.  The subsystems are then connected to each other to perform the desired operation.  The subsystem includes instruction decoder, state decoder and the control matrix.

 

The inst_decoder or the instruction decoder is the one that decodes the instruction from the instruction register. It decodes the high nibble of the instruction specifically bits 7 to 4 indicate the instruction that will be implemented by the system. Also, includes two other decoders namely C and B decoders. These decoders decodes the other 4-bits of the instruction, bits 3 to 2 for the C decoder and bits 1 to 0 for the B decoder.

 

 

• Instruction Decoder VHDL Code

library ieee;

use ieee.std_logic_1164.all;

 

entity inst_decoder is

     port (    clk  :     in std_logic;

                        inst :     in std_logic_vector(7 downto 0);

                        D          :     out std_logic_vector(15 downto 0);

                        C          :     out std_logic_vector(3 downto 0);

                        B          :     out std_logic_vector(3 downto 0));

     end inst_decoder;

 

architecture control of inst_decoder IS

     begin

 

           D_decoder : process(clk)

                 begin

                        wait until(clk'event and clk = '1');

                              case inst(7 downto 4) IS

                                    when "0000" => D <= "0000000000000001";

                                    when "0001" => D <= "0000000000000010";

                                    when "0010" => D <= "0000000000000100";

                                    when "0011" => D <= "0000000000001000";

                                    when "0100" => D <= "0000000000010000";

                                    when "0101" => D <= "0000000000100000";

                                    when "0110" => D <= "0000000001000000";

                                    when "0111" => D <= "0000000010000000";

                                    when "1000" => D <= "0000000100000000";

                                    when "1001" => D <= "0000001000000000";

                                    when "1010" => D <= "0000010000000000";

                                    when "1011" => D <= "0000100000000000";

                                    when "1100" => D <= "0001000000000000";

                                    when "1101" => D <= "0010000000000000";

                                    when "1110" => D <= "0100000000000000";

                                    when "1111" => D <= "1000000000000000";

                                    when others => D <= "0000000000000000";

                              end case;

                 end process;

 

           C_decoder : process(clk)

                 begin

                        wait until(clk'event and clk = '1');

                              case inst(3 downto 2) IS

                                    when "00" => C <= "0001";

                                    when "01" => C <= "0010";

                                    when "10" => C <= "0100";

                                    when "11" => C <= "1000";

                                    when others => C <= "0000";

                              end case;

                 end process;

 

           B_decoder : process(clk)

                 begin

                        wait until(clk'event and clk = '1');

                              case inst(1 downto 0) IS

                                    when "00" => B <= "0001";

                                    when "01" => B <= "0010";

                                    when "10" => B <= "0100";

                                    when "11" => B <= "1000";

                                    when others => B <= "0000";

                              end case;

                 end process;

     end control;

 

The state_decoder or state decoder comprises of a 3 bit counter and a T state decoder. Generally it generates T-states needed by the control matrix to output the necessary control signals. There may be one or more micro-operations and/or register transfers that are being executed in one T-state.

 

 

• State Decoder VHDL Code

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

 

entity state_decoder is

     port             (     clk        :     in std_logic;

                              clk_en  :     in std_logic;

                              clr         :     in std_logic;

                              T                 :     out std_logic_vector(7 downto 0));

     end state_decoder;

 

architecture control of state_decoder is

     signal count : std_logic_vector(2 downto 0);

     begin

 

           counter: process(clk)

                 begin

                        wait until (clk'event and clk = '1');                

                              if clr = '1' then

                                    count <= "000";

                              elsif clk_en = '1' then

                                    count <= count+1;

                              end if;

                        end process;

                

           T_states: process(count)

                 begin

                        case count is

                              when "000" => T <= "00000001";

                              when "001" => T <= "00000010";

                              when "010" => T <= "00000100";

                              when "011" => T <= "00001000";

                              when "100" => T <= "00010000";

                              when "101" => T <= "00100000";

                              when "110" => T <= "01000000";

                              when "111" => T <= "10000000";

                              when others =>      T <= "00000000";

                        end case;

                 end process;

 

     end control;

 

The cntrl_matrix or the control matrix produce control signal use by the system to execute a certain instruction. It is dependent on the instruction being executed and the T-states it undergone.

 

 

• Control Matrix VHDL Code

library ieee;

use ieee.std_logic_1164.all;

 

entity cntrl_matrix is

     port             (     D                       :     in std_logic_vector(15 downto 0);

                              C                       :     in std_logic_vector(3 downto 0);

                              B                       :     in std_logic_vector(3 downto 0);

                              T                       :     in std_logic_vector(7 downto 0);

                              Zero                  :     in std_logic;

                              CY                    :     in std_logic;

                              Sign                  :     in std_logic;

                              F                       :     out std_logic_vector(3 downto 0);

                              Sel              :     out std_logic_vector(5 downto 0);

                              Rd_ROM           :     out std_logic;

                              Ld_MAR            :     out std_logic;

                              Ld_MBR            :     out std_logic;

                              Ld_IR                :     out std_logic;

                              Ld_ACC            :     out std_logic;

                              Inc_ACC           :     out std_logic;

                              Inc_PC        :     out std_logic;

                              Ld_FLAG          :     out std_logic;

                              Ld_Z                 :     out std_logic;

                              Ld_S                 :     out std_logic;

                              Ld_CY              :     out std_logic;

                              St_PORTC         :     out std_logic;

                              Clr_TC        :     out std_logic);

     end cntrl_matrix;

 

architecture control of cntrl_matrix is

     begin

           Rd_ROM           <=  T(1) or                                                                       -- Fetch Cycle

                                           (T(4) and D(1) and C(2) and B(0)) or                        --    SUB M

                                           (T(4) and D(2) and C(1) and B(2)) or                        --    LDA address

                                           (T(4) and D(5) and C(0) and B(0));                           --    OR data

 

           Ld_MAR            <=  T(0) or                                                                       -- Fetch Cycle

                                           (T(3) and D(1) and C(2) and B(0)) or                        --    SUB M

                                           (T(3) and D(2) and C(1) and B(2)) or                        --    LDA address

                                           (T(3) and D(5) and C(0) and B(0));                           --    OR data

                                          

           Ld_MBR            <=  T(1) or                                                                       -- Fetch Cycle

                                           (T(4) and D(1) and C(2) and B(0)) or                        --    SUB M

                                           (T(4) and D(2) and C(1) and B(2)) or                        --    LDA address

                                           (T(4) and D(5) and C(0) and B(0));                           --    OR data

 

           Ld_IR                <=  T(2);                                                                           -- Fetch Cycle

 

           Ld_ACC            <=  (T(5) and D(1) and C(2) and B(0)) or                        -- SUB M

                                           (T(5) and D(2) and C(1) and B(2)) or                        --    LDA address

                                           (T(5) and D(5) and C(0) and B(0)) or                        -- OR data

                                           (T(3) and D(15) and C(1) and B(1));                         -- SHR A

                                          

           Inc_PC        <=  T(1) or                                                                              -- Fetch Cycle

                                           (T(4) and D(2) and C(1) and B(2)) or                        --    LDA address

                                           (T(4) and D(5) and C(0) and B(0));                           -- OR data

 

           Inc_ACC           <=  (T(3) and D(10) and C(0) and B(1));                         -- INC A

 

           Ld_FLAG          <=  (T(5) and D(1) and C(2) and B(0)) or                        -- SUB M

                                           (T(5) and D(5) and C(0) and B(0)) or                        -- OR data

                                           (T(3) and D(15) and C(1) and B(1));                         -- SHR A

                                          

           Ld_Z                 <=  (T(5) and D(1) and C(2) and B(0)) or                        -- SUB M

                                           (T(5) and D(5) and C(0) and B(0));                           -- OR data

                                          

           Ld_S                 <=  (T(5) and D(1) and C(2) and B(0));                           -- SUB M

                                          

           Ld_CY              <=  (T(5) AND D(1) AND C(2) AND B(0)) OR                  -- SUB M

                                           (T(3) and D(15) and C(1) and B(1));                         -- SHR A

 

           St_PORTC         <= (T(3) and D(12) and C(1) and B(1));                          -- IN C

 

           Clr_TC        <=  (T(5) and D(1) and C(2) and B(0)) or                              -- SUB M

                                           (T(5) and D(5) and C(0) and B(0)) or                        -- OR data

                                           (T(5) and D(2) and C(1) and B(2)) or                        -- LDA address

                                           (T(3) and D(12) and C(1) and B(1)) or                      -- IN C

                                           (T(3) AND D(10) AND C(0) AND B(1)) OR                -- INC A

                                           (T(3) and D(15) and C(1) and B(1));                         -- SHR A

 

           F(3)                   <=  (T(5) and D(5) and C(0) and B(0)) or                        -- OR data

                                           (T(3) and D(15) and C(1) and B(1));                         -- SHR A

 

           F(2)                   <=  (T(5) and D(1) and C(2) and B(0)) or                        -- SUB M

                                           (T(3) and D(15) and C(1) and B(1));                         -- SHR A

 

           F(1)                   <=  (T(5) and D(1) and C(2) and B(0));                           -- SUB M

                                          

           F(0)                   <=  (T(5) and D(5) and C(0) and B(0)) or                        -- OR data

                                           (T(3) and D(15) and C(1) and B(1));                         -- SHR A

 

           Sel(5)         <=  (T(5) and D(1) and C(2) and B(0)) or                              -- SUB M

                                           (T(5) and D(5) and C(0) and B(0)) or                        -- OR data

                                           (T(3) and D(15) and C(1) and B(1));                         -- SHR A

 

           Sel(4)         <=  '0';

 

           Sel(3)         <=  (T(3) and D(12) and C(1) and B(1));                               -- IN C

 

           Sel(2)         <=  T(0) or                                                                              -- Fetch Cycle

                                           (T(3) and D(1) and C(2) and B(0)) or                        -- SUB M

                                           (T(3) and D(2) and C(1) and B(2)) or                        -- LDA address

                                           (T(3) and D(5) and C(0) and B(0));                           -- OR data

 

           Sel(1)         <=  (T(5) and D(2) and C(1) and B(2));                                 -- LDA address

 

           Sel(0)         <=  T(0) or                                                                              -- Fetch Cycle

                                           (T(3) and D(2) and C(1) and B(2)) or                        -- LDA address

                                           (T(3) and D(5) and C(0) and B(0));                           -- OR data

 

     end control;

 

     The control or the control unit produces control signal with respect to the T-state and the register transfers/micro-operations code that are being executed. The control unit also determines the order in which instructions should be executed.

 

 

MATERIALS USED:

 

·          Windows based Personal Computer

·          MAX+plus II Software

 

PROCEDURES:

 

Instruction Decoder

1. Encode the VHDL code for the instruction decoder in a new text editor.
2. Save the file as inst_decoder.vhd and compile the VHDL code.
3. Create a new waveform editor for the given file and simulate.
4. Verify and record the results obtained.

 

State Decoder

1. Encode the VHDL code for the instruction decoder in a new text editor.
2. Save the file as state_decoder.vhd and compile the VHDL code.
3. Import all the nodes from the .snf file of state_decoder in a new waveform editor.
4. Save and simulate the file.
5. Verify and record the results obtained.

 

Control Matrix

1. Obtain the list of instructions for the group and their corresponding binary code.
2. Simplify all the logic functions involved for each instruction that includes the T states, Control Signals and their Boolean Expression of each micro-operation and the decoded instruction.
3. Construct the VHDL code in a new text editor.
4. Save the file as cntrl_matrix.vhd and compile the file.
5. Simulate the operation of the control matrix in a new waveform editor.
6. Verify and record the results obtained.

 

Control Unit

1.       In a new graphics editor window, insert the symbols generated for the instruction decoder, state decoder and control matrix.

2.       Make the necessary connection as shown in the experimental circuit setup.

3.       Save the file as control.gdf and compile the file.

4.       Create a new waveform editor file and import all the nodes from the .snf file of control unit.

5.       Set the necessary input signals of each instruction one at a time.

6.       Save and simulate the file.

7.       Verify and record the results obtained.

8.       Repeat procedures 5 to 7 as the need arise to finish all the assigned instructions.

 

EXPERIMENTAL CIRCUIT SETUP:

 

 

DATA AND RESULTS:

 

Instruction Decoder

 

 

 

 

 

State Decoder

 

 

 

Control Unit

 

-- SUB M Table

 

 

 

-- SUB M Waveform

 

 

ANALYSIS:

 

In the experiment, a simple control unit was implemented to generate the necessary control signals to execute the given set of instructions. Generally, it requires the binary representation of the each instruction to generate the said control signals.

 

The control unit was implemented through VHDL codes. It was divided into several subsystems namely the state decoder, instruction decoder and the control matrix. The state decoder is the one that generates the T-states undergone in executing each instruction. On the other hand, the instruction decoder decodes the binary code representing each instruction to be performed. The control matrix, which is the most important part of the control unit, generates the necessary control signals needed by the system to do certain micro-operations/register transfers to perform the whole instruction.

In every microprocessor design, timing is an important factor thus the control unit must be synchronous in operation to execute a given instruction correctly. With this, the state decoder was included in the design. The state decoder is composed of a 3-bit counter and a T-state decoder. This module is controlled by a clock with clear and a clock enable. The clock enable simply allows the counter to perform its counting sequence as long it is logically high. When this becomes low, the counting stops and retains its state. On the other hand, the clear resets the counter to its initial value, 00h. The counter outputs a 3-bit binary information that serves as an input to the T-state generator. Each count corresponds to a specific state combination generated by the T-state decoder and is inputted to the control matrix and is being set according to the step presently occupied by the clock.

The instruction decoder, which decodes the instruction to be performed, must be operated synchronously with the clock. It comprises of 3 decoders namely the D decoder, C decoder and the B decoder. The D decoder is the one that decodes the high nibble of the instruction and determines what instruction type is to be performed. In our design, the D states used are D1 for SUB, D2 for LOAD, D5 for OR, D10 for INCREMENT, D12 for IN and D15 for SHIFT RIGHT. The other 4 bits of the instruction namely the low nibble are decoded primarily by the other two decoders. Bit 3 and 2 are being decoded by the C decoder while bits 1 and 0 are being decoded by the B decoder. These decoders helps in decoding the instruction easily determining the subtype of each instruction. One of which tells whether the instruction need to access the M register while one also determines whether an immediate or register indirect is involved. The output of such module served as input to the control matrix.

Basically, the control matrix was implemented through boolean expressions. These boolean expressions determine the T-states and the decoded instruction and is simplified to generate the necessary control signals in order perform the instruction to be executed. The output signal clr_tc of this module is directly connected to the clr input of the state decoder.

CONCLUSION:

The control unit for the basic 8-bit RISC microprocessor was synthesized through the use of VHDL. It generates the necessary control signals for every component of the instruction to be performed that requires a specific micro-operation and corresponding data transfers and data operations. For this experiment, only the following instructions that were given to our group was implemented: SUB M, LDA address, OR data, INC Acc, IN C and SHR A.

In its implementation, it was divided into modules namely the state decoder, instruction decoder and the control matrix. Each module performs specific task and are connected to one another through the graphics editor to complete the whole control unit in order to perform its expected function. A lack of only a single module would ruin the whole control unit and would fail to generate necessary correct control signals or is to generate signals in the wrong time.

 

The instruction decoder is the one that determines the particular instruction to be performed. Each output of the state decoder signifies the type of instruction to be performed. It also tells where to fetch the required operands for the current instruction being performed and whether it is immediate or register direct. It is composed of three decoders namely the D decoder that decodes the high nibble of the instruction, C decoder that decodes bits 3 and 2 of the instruction and B decoder that decodes the last two bits. The D decoder is implemented through a 4x16 decoder and a 2x4 decoder for both the C and B decoder. The outputs of which is inputted to the control matrix necessary to generate the needed control signals.

 

The state decoder generates T-states that serve as the timing for the execution of several micro-operations needed to perform the whole instruction. It is important to know that such timing signals are dependent on the rising edge of the clock. Keep in mind that each instructions has different lengths of time execution. With this, the state decoder is often addressed as sequence generator. Generally, it comprised of a counter and a decoder. The counter, 3-bit counter, simply performs counting sequence needed by the decoder to generate the T-states signals. The counter continuously steps by 1 as long as it is not cleared or reset. The decoder part uses a 3x8 decoder and outputs 8 states. Each count of the counter corresponds to a single T-state. These T-states signals are the ones used by the control matrix to generate correct control signals sequentially.

 

The control matrix simply determines the necessary control signals needed by the system at a given time. It is said to be the computational part of the control unit since it generates the necessary control signals upon evaluating its inputs. Such process is done through the boolean expression obtained for each control signals as specified by the instructions. These boolean expression is set specifically by the T-state and the three outputs of the instruction decoder. Active control signals usually logically high triggers the specific functions of the registers in the data processor and others.

 

In the design process, the previous experiment regarding data transfer must be put into consideration. This is because the control signals which the control unit outputs served as the input to each registers constructed in the previous experiment in order for them to be used. A single mistake could sabotage the whole control unit since the two experiments should go hand in hand and is dependent on each other. It also is important to consider that all modules of the control unit must be synchronous with the clock since its main function is to generate control signals that are dependent to time and coordinates all the internal operations of the microprocessor.