We start with VHDL
If You have a question regarding VHDL then its quite possible that some one else has asked it before. So the very first thing to do is hop over to the VHDL FAQ and check it out...
The VHDL FAQ - This FAQ is divided into 4 sections and is posted monthly to the VHDL Newsgroup
Part 1: FAQ General (contacts, etc.)
Part 2: Lists of Books on VHDL
Part 3: Lists of Products & Services (Freewares and Commercial stuff)
Part 4: Glossary
If the FAQ proves to be inadequete you can go ask the newsgroup
comp.lang.vhdl This is the VHDL News group and this is what the FAQ for this newsgroup says
"The newsgroup comp.lang.vhdl was created in January 1991. It's an international forum to discuss ALL topics related to the language VHDL which is currently defined by the IEEE Standard 1076/93. Included are language problems, tools that only support subsets etc. but NOT other languages such as Verilog HDL. This is not strict - if there is the need to discuss information exchange from EDIF to VHDL for example, this is a topic of the group. The group is unmoderated. Please think carefully before posting - it costs a lot of money! (Take a look into your LRM for example or try to search http://www.Deja.com/usenet - if you still cannot find the answer, post your question, but make sure, that other readers will get the point). "

Who wouldnt want a good low cost setup for dirtying their hands in HDL Design? Here is a starter kit.

Editor: The choice of editors is a very controversial subject, you may want to check out what others have to say about this by searching google groups for "VHDL editor" and also the stuff listed in the FAQ( part 3 ). For unix buff you can always go in for emacs/Xemacs and download the VHDL mode. Or else stick to good old vim and use the necessary stuff for syntax highlighting.
For windows users I have not tested any of the freely available editors.. but a port of emacs for windows is available.
Simulators: When It comes to simulators The preferred choice when the budget is good is the Industry Standard Modelsim. For those with limited budgets You can try Activevhdl.For those who believe that the good things in life come free... there is always the VHDL compiler from vanilla cad tools for linux and VHDL Simili from symphonyEDA for windows Until we see the guys at freehdl and gnu eda make any progress that is.
Synthesis: Unfortunately I cant think of any cheap/free good synthesis tools which can be used... the snapshots at mycad look good, but I have yet to try some thing other than synopsys until I find some really good free stuff you can use the stuff listed in the newsgroup FAQ and if you find anything worthy send me a mail...

Learning VHDL

There are quite a few good VHDL Tutorials and books available on the web
This list is but a drop in the ocean
VHDL Tutorial A javascript based tutorial which uses javascript to open new windows by Prof. Dr.-Ing. Wolfram H. Glauert of "Universität Erlangen-Nürnberg Lehrstuhl für Rechnergestützten Schaltungsentwurf"
VHDL Verification Course Suitable for those who already know the syntax and want to use the language for verification purpose
A Hardware Engineer's Guide to VHDL This VHDL tutorial assumes no prior knowledge of HDLs.
VHDL Language Guide Covers Language Overview, A First Look at VHDL, Objects, Data Types and Operators, Using Standard Logic, Concurrent Statements, Sequential Statements, Modularity Features, Partitioning Features, Test Benches, Keyword Reference, Examples Gallery

VHDL Tools

Code Generators

Statecad FSM to VHDL/Verilog generator (30days eval available)
CRC Tool Generates synthesizable CRC code in VHDL and Verilog

Models

LEON-1 VHDL model The LEON core is a SPARC* compatible integer unit developed for future space missions. It has been implemented as a highly configurable, synthesisable VHDL model. To promote the SPARC standard and enable development of system-on-a-chip (SOC) devices using SPARC cores, the European Space Agency is making the full source code freely available under the GNU LGPL license. Strasbourg UniversityAn ftp site containing VHDL utilities, papers, and VHDL code.

Other resources

hamburg VHDL Archive VHDL documents (FAQ, introductions to VHDL, etc.), VHDL-related papers, and public domain utilities.

One of the best places to look for HDL related information is the various online Directories

Google Web Directory - Science > Technology > Electronics > Design > Verilog_and_VHDL_Tools
Google Web Directory - Computers > Programming > Languages > VHDL

Programming > Languages > VHDL

Technology > Electronics > Design > Verilog and VHDL Tools

Discuss This section and any questions on the VHDL Language at the VHDL discussion board

Synthesis

VHDL SYNTHESIS TUTORIAL A tutorial on synthesis By Bob Reese of Electrical Engineering Department Mississippi State University.

Discuss synthesis tools and synthesis related issues at the synthesis page

VERILOG

Before going to the newsgroup at comp.lang.verilog it would be advisabe to check the FAQ while teh original FAQ is at http://www.landfield.com/faqs/verilog-faq/ It has been many moons since it has been updated :-( so many now make way to http://www.angelfire.com/in/verilogfaq/ which is the updated version of the previous