8086/8088 Microprocessor

subsubsectionInstruction Set Architecture The Instruction set architecture of 8086/8088

Processor Model

The following shows the 8086 architecture.

• BIU(Bus Interface Unit) generates the memory and IO addresses for the transfer of data and instructions and realize these transfers.
• EU(Execution Unit receives program instruction codes and data from the BIU, executes these instructions and stores the results either in the general registers or output them through the BIU. EU has no connections to the system busses. It receives and outputs all its data through the BIU.

The only difference between the 8086 and the 8088 microprocessors is that BIU of 8088 can transfer only 8 bits data at one time.

Fetch and Execute Cycle

• BIU outputs the contents of the IP onto the address bus.
• Register IP is incremented by one or more than one for the next instruction fetch.
• the instruction is passes to the queue. This is a 8 byte first-in-first-out queue.
• EU draws an instruction.
• While EU is executing this instruction, the BIU proceeds to fetch a new instruction. BIU will fill the queue with several new instructions before the EU is ready to draw its next instruction.
• The cycle continues.

Pin-Outs and the Pin Functions

The Pin-Out

The following figure illustrates the pin-outs of the 8086 and 8088 microprocessors. From the outside, there is virtually no difference betveen these two microprocessors- both are packaged in 40 pin dual in-line packages(DIPs).

Pin Functions

We will see the pin functions in different categories. CPU can operate in two modes:minimum mode and maximum mode.

Minimum mode

MN/MX' pin is connected to +5V. Used in small systems including only one CPU.

Maximum mode

MN/MX' pin is connected to ground. Used in large systems and systems with more than one processors.

Minimum Mode versus Maximum Mode

Minimum mode operation

Least expensive way to operate 8086 microprocessors, because all the control signals for the memory and IO are generated by the microprocessor. They are identical to those of 8085A.

Minimum mode signals:

Address/data/status
AD15-AD0	address/data bus	Bidirectional, 3-state
A19/S6-A16/S3	address/status bus	output,3-state
Handshaking for data read/write
RD'	read from memory/IO	output,3-state
READY	ready signal	input
M/IO'	select memory or IO	output,3-state
WR'	Write to memory/IO	output,3-state
ALE	Address latch enable	output
DT/R'	data transmit/receive	output
DEN	Data bus enable	output
BHE'/S7	bus high enable	output
Interrupt signals
INTR	interrupt request	input
NMI	non-maskable interrupt	input
RESET	reset	input
INTA'	interrupt acknowledge	output
Bus access control
HOLD	Hold request	input
HLDA	Hold acknowledge,whether the CPU is in hold state	output
Others
SSO'	a status bit combined with IO/M' and DT/R'	output
TEST'	test pin tested by WAIT instruction	input
MN/MX'	Minimum/maximum mode, 5V	input
CLK	clock pin for basic timing signal	input
Vcc	power supply, +5.0V,$\mp 10\%$
GND	ground connection, 0V

During the hold acknowledge, AD15-AD0,A19/S6-A16/S3,RD',M/IO',WR' pins are in high-impedance state.

• Status bit s6 always remains a logic 0, bit s5 indicates the condition of the IF flag bit, and s4 and s3 show which segment is accessed during the current bus cycle.

  Function of status bits s3 and s4

  S4	S3	Function
  0	0	ES, Extra segment
  0	1	SS, Stack Segment
  1	0	CS or no segment
  1	1	DS, Data segment

• Bus cycle status

  The 8086/8088 processors use the memory and IO in periods of time called bus cycles. In 8086/8088 there are three basic cycles using data bus:

  • Read bus cycle. reading instructions and data from memory or IO.
  • Write bus cycle. Writing data to memory or IO
  • Interrupt cycle. Getting interrupt vectors from interrupting devices. This is also a read operation.

  IO/M'	DT/R'	SSO'	Function
  0	0	0	Interrupt acknowledge
  0	0	1	Memory read
  0	1	0	Memory write
  0	1	1	Halt
  1	0	0	Opcode fetch
  1	0	1	IO read
  1	1	0	IO write
  1	1	1	Passive

Maximum mode operation

Maximum mode signals

Address/data/status
AD15-AD0	address/data bus	Bidirectional, 3-state
A19/S6-A16/S3	address/status bus	output,3-state
Handshaking for data read/write
RD'	read from memory/IO	output,3-state
READY	ready signal	input
BHE'/S7	bus high enable	output
S2',S1',S0'	status/handshake bits indicating the function of the current bus cycle	output
Interrupt signals
INTR	interrupt request	input
NMI	non-maskable interrupt	input
RESET	reset	input
Bus access control
RO'/GT1',RO'/GT0'	request/grant pins for bus access	bidirectional
LOCK'	used to lock the bus, activated by LOCK prefix on any instruction	output
Others
QS1,QS0	queue status	output
TEST'	test pin tested by WAIT instruction	input
MN/MX'	Minimum/maximum mode, 0V	input
CLK	clock pin for basic timing signal	input
Vcc	power supply, +5.0V,$\mp 10\%$
GND	ground connection, 0V

• Bus control functions

  s2'	S1'	S0'	Function
  0	0	0	Interrupt acknowledge
  0	0	1	Memory read
  0	1	0	Memory write
  0	1	1	Halt
  1	0	0	Opcode fetch
  1	0	1	IO read
  1	1	0	IO write
  1	1	1	Passive

Maximum mode operation differs from minimum mode in that some of the control signals must be externally generated. This requires additional circuitry, however, a chip -the 8288 bus controller- designed for this purpose is available.

Bus Cycles and Handshaking

The 8086/8088 processors use the memory and IO in periods of time called bus cycles. In 8086/8088 there are three basic cycles using data bus:

• Read bus cycle. reading instructions and data from memory or IO.
• Write bus cycle. Writing data to memory or IO
• Interrupt cycle. Getting interrupt vectors from interrupting devices. This is also a read operation.

The following is the simplified time diagram of the common bus signals to read and write data from/to memory and IO.

Figure 21: Simplified diagram of read bus cycle

Figure 22: Simplified diagram of write bus cycle

Figure 23: Simplified diagram of interrupt acknowledge cycle

8086 Bus Interface

DC Characteristics

Every pins on the processor has a fan-out. I.e. there is an upper limit on the number of units that can be connected tto the pins. If, in a system, the number of units exceeds this limit, then the bus signals must be buffered to increase this limit.

The followings are the input and output DC characteristics of the 8086/8088 microprocessors.

Input DC Characteristics

Logic level	Voltage	Current
0	0.8V max	$\pm 10\mu A$ max.
1	2.0V min	$\pm 10\mu A$ max.

Output DC Characteristics

Logic level	Voltage	Current
0	0.45V max	$2mA$ max.
1	2.4V min	$-400\mu A$ max.

This means if the sink current exceeds $2mA$, then the output voltage exceeds 0.45V. If the source current exceeds $400\mu A$ then the output voltage drops below 2.4V.

Figure 24:

Let calculate the maximum number of 74LSXXX devices that can be connected to the output pins of the 8086 processor.

The input characteristics of 74LSXXX devices

Logic level	Voltage	Current
0	0.8V max	$20\mu A$ at 0.8V
1	2.0V min	$-4mA$ at 2.0V

Demultiplexing the Buses

Bus Buffering and Latching

Ready, Wait States, Ready Circuits

The not READY signal from the IO and memory components causes wait states for slower memory and IO components. A wait state(Tw) is an extra clocking period, inserted between T2 and T3, that lengthens the bus cycle.

The READY input is sampled (by the processor) at the end of T' and ,if applicable, in the middle of Tw. If READY is at logic 0 at the end of T2, then T3 is delayed and a Tw is inserted. READY is next sampled at the middle of Tw to determine if the next state is again a Tw or T3.

Figure 25: Read cycle with two ready state

A circuit that will cause between 0 and 7 wait states are illustrated in the following figure:

Figure 26: A READY circuit

To see if this circuit really works, let see the timings.

Figure 27: Timing of the circuit

TCLRL

The delay from the beginning of T2 to the activation of RD' signal.($\bf\leq 165ns$)

Ta

The propogation delay from the RD'=0 to CLR'=1. This is the propogation delay of 74LS13 AND gate from low input to high output.($\leq 15ns$)

Tb

The setup time from the CLR high to CLK of the 74LS164 shift register.(Clear release time$\leq 30ns$)

Tc

The delay from CLK rising edge to Qa high and the delay from CLK rising edge to Qb high.(no information)

Td

The delay from Qb high to READY high. Equal to the propogation delay of the OR gate 74LS32.($\bf\leq 15ns$)

TCLCH

CLK low period.( $\bf\geq 118 ns$)

Now the question is "is this circuit really works as specified in the timing diagram?". To see this let investigate the timing where the CLK and CLR' input to the shift register rises.

Time from the beginning of T2 to $CLR'\uparrow=TCLRL+Ta\leq 165ns+15ns=180ns$

Time from the beginning of T2 to $CLK\uparrow=TCLCH\geq 118ns$

As seen for the extreme cases, the CLR' signal is still active when the CLK is in rising edge state. So the timing diagram of this circuit can not be the given. On the other hand, for some other cases(not extreme) this circuit works as proposed.

Conclusion: It is not a reliable READY circuit.

Instruction Execution vs Bus Cycles

Each instruction must be fetched before executed. Also instructions need to read and write data to the memory/IO units. BIU(Bus interface Unit) of 8086 is responsible to do all read and write operations and it does this by read and write cycles. The following figure illustrates this.