Main Memory Interface

The main memory of a computer system should be fast enough to not degrade the performance of the system. To achieve this, the semiconductor type memories are used as main memory.

Here we will investigate the three common types of memory:

• read-only memory(ROM)
• static read-write memory or random access memory(SRAM)
• dynamic read-write memory or random access memory(DRAM)

Among them ROM is a non-volatile memory type. I.e. they retain their contents when the power goes off. On the otherhand, SRAM and DRAM type devices loss their contents when the power goes off, because of the technology used.

Pin connection

In fact all of these devices are random access memories. I.e. each byte or word has an address and can be accessed randomly. The following is a pseudo memory component showing the address, data and control connections.

For ROM and SRAM, the above device has nxm bits. Today the capacity of one chip SRAM memories are less than 1MB, however, there are 128Mbits DRAM memories.

In most of the RAM devices, the same pins are used for both read and write data. So at one time only a read or write operation is possible. Some other devices (e.g. some DRAM devices) has seperate data pins for input and output, but still they can do only read or write at one time.

Most of the memory devices produced has an input-sometimes more than one-that selects or enables the memory device. It is most often calles a chip select(CS'), chip enable(CE) or simply select(S) input. The other input(s) are used to retrieve or store data.

An example function table:

CS'	OE'	WE'	D0-Dm
1	x	x	Z(high impedance)
0	x	0	Data in
0	0	1	Data out
0	1	1	Z(high impedance)

The following figure illustrates the read and write timing for a typical memory device.

Figure 35: Read timing

Figure 36: Write timing

General block diagram.

ROM memory

In ROM, the data are permanently stored. They are available in many forms.

• ROM. Its content can not be erasable.
• PROM(Programmable read only memory. Once programmed, they can not be erased.
• EPROM.(erasable programmable ROM). Erasable by ultraviolet lights.
• EEPROM(electrically erasable programmable ROM). Known also as flash memory, EAROM(electrically alterable ROM) and NOVRAM(nonvolatile RAM). These devices are electrically erasable but require more time to erase than a normal RAM.

SRAM memory

DRAM memory

• In DRAM each cell is constructed by a transistor and a capacitor. So DRAMs are available in much larger sizes up to 256MB.

• Each bit cell in DRAM memory retains data for only 2 or 4ms on an integrated capacitor. After 2 or 4ms, the content of the cells must be rewritten(refreshed), because the capacitors lose their charges.

• Because of large capacity, DRAMs require so many address pins that the manifacturers have multiplexed the address pins. The number of address pins are half of the required pins. Usually two special pins RAS'(Row address strobe) and CAS'(column address strobe) are used to give the row address and column address respectively. The following is an example timing diagram.

  The following circuit diagram shows the 41256 DRAM pins and an address multiplexer for this type of chips. The propagation delay of the multiplexers must be greater than $t_h(RA)$ in order to work.

Other types of main memory

RAM type devices

Many attempts have been made to built nonvolatile RAMs. The ideal nonvolatile RAM should be as fast as ROM with similar cost and packing density but with the read/write capability and the simplicity of use of SRAM. None of the following devices approaches this ideal, however each is used in situations where a nonvolatile read/write memory is required.

Magnetic Core Memory

The memory used in earlier electronic computers(pre-1970s) was magentic core memory. It is still used in some military systems where its nuclear radiation resistance is a major advantage. It consists of tiny doughnuts of ferromagnetic material, each of which is magnetized circumferentially. The direction of the magnetic flux determines the binary value.

Battery-Backed CMOS RAM

The power consumption of RAM implemented in CMOS technology is low enough that the use of battery backup to provide nonvalatility is feasible. CMOS RAM chips have usually an stand by state. In stand by state, they do nothing than to retain their contents and spend a few microamperes only.

Shadow RAM

RAM chips are available that incorporate EEPROM backup along with standard SRAM memory matrix in the same integrated circuit package. During normal use, this so-called shadow RAM has all the characteristics of a SRAM. However, if a control pin is activated( e.g. as a result of a power failure), the chip automatically dumps the current content of the RAM matrix into the EEPROM in about the order of ten millisecons. When the chip power is restored, the internal circuitry automatically restores the RAM to the content of the EEPROM.

Serial Devices

Magnetic Bubble Memory

Charge Coupled Device

Associative Memory

Address Decoding

Memory Modules

If only one memory device are to be connected to a bus, then it can easily be realized by connecting the address bus to the address lines, data bus to the data lines and control bus to control lines. However, this is not usually the case. A ROM device is a must in a computer system, so such a system can only be realized by a ROM memory device. If RAM is also required, the number of memory component must be greater than one. Also usually the available memory IC's does not meet the needs. I.e. there must be more than one RAM memory device to have the desired memory capacity. For example, if the desired capacity is 1Mbyte and the there are 256kB chips at hand, then four of these units are connected together to get such a capacity.

SRAM Memory Modules

The following figures illustrates the desired memory module and the available memory device.

The addressing of the memory module can be established by means of a table that specifies the memory address assigned to each chip.

As seen the first chip and second chip must be activated when the address is between 00000h-3ffffh. The following table illustrates this.

Address	values of A19-A0	Chip activated
0h-3ffffh	00xx xxxx xxxx xxxx xxxx	MD0,MD1
40000h-7ffffh	01xx xxxx xxxx xxxx xxxx	MD2,MD3
80000h-bffffh	10xx xxxx xxxx xxxx xxxx	MD4,MD5
c0000-fffffh	11xx xxxx xxxx xxxx xxxx	MD6,MD7

Figure 37: A design of the memory module

The following is function table of the address decoding circuitry.

A18	A17	CS0,CS1	CS2,CS3	CS4,CS5	CS6,CS7
0	0	0	1	1	1
0	0	1	0	1	1
0	0	1	1	0	1
0	0	1	1	1	0

Simple Gate decoder

Using decoder chips

ROM Address Decoder

Programmable Array Logic Devices

8088 (8 bit) Memory Interface

When the 8086/8088 CPU is reset, it starts from the location FFFF0h. So there must be a program there and this must be a nonvolatile memory. The following illustrates a memory system for a 8088 CPU where each of SRAM IC and ROM IC are shown below.

8086 (16 bit) Memory Interface

16 bit bus control

The unique problem with 16 bit data bus is that the 8086 must be able to write data to any 16 bit location-or any 8-bit location. This means that the 16 bit data bus must be divided into two seperate sections(banks) that are 8-bit wide and the microprocessor can access to either half at seperate times(8-bit operation) or at the same time(16 bit operation).

The 8086,80186,80286 and 80386SX use $\overline{BHE}$ signal(Bus high enable) to access the high bank and A0 signal to access the low bank. The following table illustrates the function of these pins.

BHE'	A0	Function
0	0	Both banks are enabled for a 16-bit transfer
0	1	High bank enabled for an 8-bit transfer
1	0	low bank enabled for an 8-bit transfer
1	1	No banks enabled

Example: Design a module providing 128Kx16 bits using 62256 32Kx8 SRAM. The following figure illustrates the desired module and the 62256 SRAM

The following is the memory map of the module.

In the module we prefer to use MBHE' and MA0 to determine the 8-bit and 16-bit transfer as mentioned before. While writing to such a module, i.e. while MWR'=0, the function table is as follows:

MWR'=0
MRD'	MBHE'	MA16-MA0	The chip to be active
0	x	x xxxx xxxx xxxx xxxx	No chip
1	0	0 xxxx xxxx xxxx xxx0	SR0,SR1
1	0	0 xxxx xxxx xxxx xxx1	SR1
1	0	1 xxxx xxxx xxxx xxx0	SR2,SR3
1	0	1 xxxx xxxx xxxx xxx1	SR3
1	1	0 xxxx xxxx xxxx xxx0	SR0
1	1	0 xxxx xxxx xxxx xxx1	No chip
1	1	1 xxxx xxxx xxxx xxx0	SR2
1	1	1 xxxx xxxx xxxx xxx1	No chip

While reading there may be two approaches:

• For 8-bit transfer only the appropriate bank would be active. Then the function table would be the same with the above except the role of MRD' and MWR' signals are exchanged.

• For 8-bit transfer both of the banks are active. This is possible because 16 bit 80x86 processors read only the byte of data they need at any given time from half of the data bus. If 16-bit sections of data are always presented to the data bus during a read, the microprocessor ignores the 8-bit section it doesn't need without any conflicts or special problem. So we can adopt this method for a memory module to be used with 80x86 processors. Then the function table would be as follows:

  
  
  
  

  MRD'	MWR'	BHE'	MA16-MA0	The chip to be active
  0	0	x	x xxxx xxxx xxxx xxxx	No chip
  0	1	x	0 xxxx xxxx xxxx xxx0	SR0,SR1
  0	1	x	0 xxxx xxxx xxxx xxx1	SR0,SR1
  0	1	x	1 xxxx xxxx xxxx xxx0	SR2,SR3
  0	1	x	1 xxxx xxxx xxxx xxx1	SR2,SR3

  
  
  
  

If we prefer to use the last approach the full function table would be as follows:

MWR'	MRD'	MBHE'	MA16-MA0	chip to be active
0	0	x	x xxxx xxxx xxxx xxxx	No chip
0	1	0	0 xxxx xxxx xxxx xxx0	SR0,SR1
0	1	0	0 xxxx xxxx xxxx xxx1	SR1
0	1	0	1 xxxx xxxx xxxx xxx0	SR2,SR3
0	1	0	1 xxxx xxxx xxxx xxx1	SR3
0	1	1	0 xxxx xxxx xxxx xxx0	SR0
0	1	1	0 xxxx xxxx xxxx xxx1	No chip
0	1	1	1 xxxx xxxx xxxx xxx0	SR2
0	1	1	1 xxxx xxxx xxxx xxx1	No chip
1	0	x	0 xxxx xxxx xxxx xxxx	SR0,SR1
1	0	x	1 xxxx xxxx xxxx xxxx	SR2,SR3
1	1	x	x xxxx xxxx xxxx xxxx	No chip

The activation of chips can be done in various ways. For example to activate a chip while writing the WE' and CS' signals must be activated. I.e. to deactive a chip deactivating only one of these signals are enough. The following is a realization of the above function table.

Dynamic RAMs

DRAM Timing

• The row address is applied to the address connections by the $\overline{RAS}$(rpw address strobe) signal.This strobe enters the row address into an internal latch, where it is held during a memory cycle.
• After $t_{RCD}$ time, the column address and the $CAS'$(column address strobe) is applied. This strobe sends the column address into an internal register where it is held for the current memory cycle. It also causes the memory device to begin to access data.
• A read signal applied during the current cycle causes the contents of the selected location to appear at the output pin after $t_{CAC}$ and $t_{RAC}$ time. The data at the output pin remains valid and stable until the CAS input becomes high.

DRAM Refreshing

The data in each cell of a dynamic RAM is held only for 2-8ms. For the 51100x, the $t_{REF}$ parameter(=8ms) specifies the maximum time period during which all the cells must be refreshed at least once.

RAS' only Refresh

A RAS' refresh cycle begins with the assertion of the RAS' input. The CAS' input is held high. The WE' input may be low or high. The $A_0-A_9$ inputs are set to the row address. This causes all words(or cells) in that row to be refreshed. A refresh cycle can be initiated once every $t_{RC}$ time units. Thus to refresh all the cells in the 51100x, a total of 512 refresh cycles are needed. This would require a total of about $512x165ns=84.48us$ to refresh all the cells in a chip.

Hidden Refresh

The hidden refresh cycles are performed during a normal read cycle. Once the row and column strobes have been asserted, and the desired location addressed, RAS' is negated, the row address supplied and RAS' is asserted again. This starts the refresh of all the cells within the selected row. However, during refresh, the data read from the cell selected just prior to the refresh, remains valid on the $D_{OUT}$ line.

Multiple hidden refresh cycles can be executed one after another. However, this is limited by the maximum width of the CAS' pulse.

Burst and Distributed Refresh

During a refresh, the chip can not be used for the read or write data. The method of refreshing the entire memory before the microprocessor can resume the normal access, is known as burst or concantrated refresh.

Another way to refresh the memory is by using distributed refresh. In this case, the refresh control circuit performs one refresh cycle in $t_{REF}$ time period. However, the refresh cycles are distributed over time as shown in the figure.

Pseudo Static RAMs and Automatic Refresh

Pseudo static RAMs(PSRAMs) are dynamic RAMs with built in refresh logic. An example is shown.

Fast access modes

Many DRAM chips provides extra modes for fast access of data in a row. One chip provides one of the following three modes of operation.

Page mode operation

Nibble mode operation

Static Column Mode operation

DRAM Interface

In DRAM interface there are two things that is different from a SRAM interface.

• DRAM must be refreshed and during refresh it is not possible to read/write from/to the memory.
• Usually the address inputs to the DRAM are multiplexed.

The last problem can easily be solved with multiplexers as shown below.

The first problem can be solved in many ways. However, usually the DRAM interface has a new signal REFRESH whixh is driven by an refresh circuitry. The following diagram illustrates the connection of a 1Mx8 DRAM module to the common bus.