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Subsections

Introduction/Background

History

Single Processor Microcomputer Organization

Each digital computer system provides

A microcomputer is a computer which uses a microprocessor as a CPU. A microprocessor is a CPU in one integrated circuit.

A microcomputer is usually built around a common bus. The following illustrates the general structure of typical microcomputer architectures.

Figure 1:
\begin{figure}\centering\epsfig{figure=pics/genarch.eps}\end{figure}

The input/output units are put there to be able to enter/get data to/from the microcomputer. The environment of a sytem may be other systems, so among these devices there are network units. The putting/getting data and controlling these devices are done via ports. Ports are the special registers in these units.

Figure 2: An IO units provides ports
\begin{figure}\centering\epsfig{figure=pics/ports.eps}\end{figure}

Each port has an address. From the view of the CPU hardware, there is no distinction between a data port and control port. The number of ports, the function of each port etc is depend on the architecture of the unit and the programmer writes programs according to this information. I.e. a low level programmer must know these details to write programs using a particular unit.

There are other units in a computer system which are part of the system but still seen as an IO unit. In fact, in most of the system, writing/reading to/from ports is the only way for CPU to control/interact with various devices of the system,so almost every devices in the system provides ports, such as interrupt subsystem,memory management, clock, DMA(Direct Memory Access) subsystem etc. So the name IO units are used for all of these units not for only devices used to interact with the environment.

The main memory is used to keep currently executing programs and currently used data. This is a von Neumann architecture because the same memory is used both for programs and data. Although any physical medium that is capable of storing digital data can be used as main memory, it is usually built using semiconductors. The first main memories used were magnetic mediums. However, they were slow. Today, the slow but cheap and large memories are used as secondary storage devices, such as magnetic disk, optical disk, magnetic tape etc. In todays most of the architecture, they are connected to the system just like an IO unit. So from the view of the CPU, they are just IO units.

Usually, the IO devices/interfaces are directly connected to the common bus. In that case, the organization look likes in the figure 3.

Figure 3:
\begin{figure}\centering\epsfig{figure=pics/commonbusarc.eps}\end{figure}

The currently executed programs reside in main memory. The instructions contained in the currently executed programs are first transferred to the CPU and then executed. According to these instructions, CPU transfer/copy data among storage units(IO ports, memory locations, internal registers,ALU) in various places and/or alter them in ALU. The modification of data is achieved by sending one or more data to ALU. Then the manipulated result is transferred to registers.

Figure 4: Manipulation of data
\begin{figure}\centering\epsfig{figure=pics/datamanip.eps}\end{figure}

Before executing a program, the program are brought to the main memory by another program called "loader". Note that except interrupts and DMA, anything in a system is usually done by instructions.

To access a memory location or IO device register, the processor would transmit the address, in binary form, on the address bus. The size of the address bus puts a limit on the number of IO ports and memory locations but the number of IO ports are usually much smaller than that of memory locations, so address bus size is said to determine the maximum size of the system's main memory.

The data bus is used to send or receive data among the devices. The addressed devices respond by accepting or putting data on the data bus.

The control bus is used to control data transfer, such as the direction of transfer etc.

Communication

We encounter the need for information transfer not only between the microprocessor and the other units in a microcomputer system, but almost in every device using digital technology. Here we will investigate some general methods for information transfer between digital devices.

Two Units

Think about two units one is sender and the other is receiver.

Figure 5:
\begin{figure}\centering\epsfig{figure=pics/onesender1.eps}\end{figure}

Assume the sender wants to send n bits data to the receiver.To do this there must be a medium to carry information between these two units. Among these mediums:

Protocols

To send or receive information, the sender and receiver must understand each other. For example if sender send a signal "1" as a high voltage level, the receiver must also treat a high voltage level as "1". I.e. both sender and receive must speak the same "language". This is called protocols.

Coding 0 and 1

Another problem is how to code digital data.

In the units of a microcomputer, usually copper wires are used and the bit information 0 and 1 is coded as distinct voltage levels on a pair of wire.

Serial vs Parallel Transfer
There are two extreme way for transfer n bit data:

The methods which are between these extreme cases can also be used. For example if $m+1$ wires where $m<n$ are used, then at an instance only $m$ bits can be transferred but the transfer time will be $t_s/m$ where $t_s$ is the transfer time of serial case.

Figure 8:
\begin{figure}\centering\epsfig{figure=pics/sendbetween.eps}\end{figure}

Sending "no information" information

Another problem is that the receiver must detect the "no information" case as well as "0" and "1". This is an additional information that must be also be send to the receiver.

There may be many ways to send "no information" information. The followings are some of them.

Figure 9: A circuitry used to code "no information" case
\begin{figure}\centering\epsfig{figure=pics/onesender2.eps}\end{figure}

Ensuring Successful Data Transfer

If the sender put data on the data bus, then is this data has been reached and received by the receiver? If the receiver guarantees to record a data within, say, $\delta$ time, then the keeping the data on the bus for at least $\delta$ time will solve this problem.

\begin{figure}\centering \end{figure}

The figure 10 illustrates a simple circuit to write a data to a register in the unit B

Figure 10: A recording circuit in unit B
\begin{figure}\centering\par\epsfig{figure=pics/atobsimple.eps}\end{figure}

However, if this can not be guaranteed or the timing between the devices is different then some feedback is required from the receiver side.

The most simple approach is to send data on the medium then get a feedback from the receiver which informs that the data is received successfully. I.e. the receiver must send an information to the sender. The following is an example architecture that uses this approach.

Here, the "no information" case and the feedback uses dedicated lines.

\begin{figure}\centering\epsfig{figure=pics/twohandline.eps}\end{figure}

H1 is used to code "no information" case and H2 is used for feedback.

H1 H2 Coded case
0 0 Unit A has no information to send, Unit B has not received data succesfully
0 1 Unit A has "no information", Unit B has received data successfully
1 0 Unit A has put data on the data bus, Unit B has not received it yet
1 1 Unit A has put data on the data bus, Unit B has received it.

The following illustrates a successful data transfer:

Figure 11: A data transfer
\begin{figure}\centering\epsfig{figure=pics/twohldatatr.eps}\end{figure}

If the sender is guaranteed to receive the information on H2 within, say $\delta$ times, then the following data transfer scheme is also possible.

Figure 12: Another way of data transfer
\begin{figure}\centering\epsfig{figure=pics/twohldatatr2.eps}\end{figure}

Two Way Transfer

Now consider the case where the data transfer can be in two way: from A to B or from B to A. Now all the problems that exist for from A to B transfer are exists for the transfer from B to A.

There may be two possibility in two way transfer:

Collision in Half Duplex Communication

In Ethernet, even with only two devices, collision problem is solved as follows:

Every unit on the bus has capable of detecting collision. If a unit send a data and detect collision, then it waits for a random time and then try again. This is repeated until there is no collision or the number of tries reaches a predetermined limit.

Another solution to this problem is to let only one unit to initiate transfer. This approach is known as master-slave configuration and investigated in the following section.

Many Units around a Common Bus

Figure 14: Many units around a common bus
\begin{figure}\centering\epsfig{figure=pics/multdevices1.eps}\end{figure}

In this configuration, since there is only one bus, there can be only one transfer at a time. I.e. an half duplex communication. Again, if more than one unit initiate transfer at the same time, a collision occurs and there must be some mechanism to resolve this. One solution to this is to trying transfer after waiting a while as mentioned before.

Here, there is another problem. Since, the bus is common, every unit on the bus receives all the information. So each source must send an additional information about the destination of data. I.e. sender must also send the destination address. If this information is coded on seperate wires, then these wires are named as an address bus.

One Master-Many Slave

In this scheme, there is a master which can transfer to/from all slaves. To not allow collision, only master can initiate a transfer. If a slave unit has data to transfer, it inform the master and then master initiates a transfer from the slave. In one variation of this, no slave/slave transfer is allowed. Only master/slave transfer is possible.

Many Master-Many Slaves

Most systems are designed to have more than one master. Each master can communicate with each slave, but master-master and slave-slave transfer is not allowed. Such systems use slave units to communicate to each other. For example, one master writes to a slave unit and another master reads this data from it. However, there is a collision between masters. This problem is usually solved by adding a super-master as the follows: each master that are going to initiate a data transfer, first inform this to the super-master unit. This unit gets all such signals from masters, but gives only one master an authority to use the data bus. Usually one of the master are assigned to be the super-master. However, a special unit called bus arbiter can also be used as a super-master.

Of course, such a system requires additional lines to handle additional cases.

Single Processor Microcomputer Bus Architecture

The microcomputers usually are built around one common bus. For fast operation, the memory must be close to the CPU as much as possible. The IO units can be connected to this bus or a sperate bus for IO units can be build. The following illustrates such a design mixing each method.

Figure 15: A microcomputer with two bus
\begin{figure}\centering\epsfig{figure=pics/twobussys.eps}\end{figure}

Single processor microcomputers may be a one or more master systems. The general purpose single CPU microcomputer systems usually have two masters: a CPU and a DMA(Direct Memory Access) unit. DMA units are responsible to do the direct transfer of data between the main memory and any IO unit. When a DMA unit want to gain the control of the bus, then it informs this to the CPU . The CPU then gives permission to the DMA unit and deactivates its bus signals. Here the processor plays the role of a super master . When the DMA unit gets the permission, then it activates the bus to do the necessary transfer.

In microcomputers, only master can initate a transfer and no slave/slave transfer is allowed. The master write/read something to/from a port/memory location in the slave units. If a slave unit has a data to be send or want to get data from the CPU, it must first inform this to the CPU(how?).

Address Selection

In all of these schemes, the address lines carry only the slave address(a memory location or port). In 80x86 systems, the IO port and memory locations have different addresses and there are additional signals to handle this. Each IO unit can have one or more memory location or port. So, actually, a slave unit can have multiple address. However, single or multiple, a slave unit must do a transfer only when it is addressed. The followings are the two methods to achive this.

In fact, the only difference between the first and the second method is that in the first method, the address selection circuitry takes place in the slave unit. Usually both of these methods are used simultaneously. So there is a hierarchy of address selection. A unit uses an address selection circuit to select its subunits and each subinit can have its own address selection to select its own subunits and so on.

Signal Transition among the Logic Gates and other digital units in a microcomputer

TTL Circuits

The TTL Logic gates are widely used to construct digital devices. The following figures shows two circuits: the NAND gate with totem-pole output and the NAND gate with open collector.

Figure 18: Totem-Pole output
\begin{figure}\centering\input{pics/ttl-nand-tp.eepic} \end{figure}

Figure 19: Open Collector
\begin{figure}\centering\input{pics/ttl-nand-oc.eepic} \end{figure}

Voltage Levels

Today most of the digital circuits operate between two voltage levels, one of which is HIGH(logic 1) and the other is LOW(logic 0).

Figure 20: Logic Levels
\begin{figure}\centering\input{pics/logiclev.eepic} \end{figure}

The following is the voltage levels of TTL gates accepted as standard.

Symbol margin Expl.
$V_{OH}$ 2.4V-5V Voltage level for output HIGH
$V_{OL}$ 0V-0.4V Voltage level for output LOW
$V_{IH}$ 2V-5V Voltage level for input HIGH
$V_{IL}$ 0V-0.8V Voltage level for input LOW

Fan-in, Fan-out

While connecting the gates together, there are limitations. The fan-out of a digital circuit is the maximum number of component that can be connected to one single output without disturbing the digital signal. To see this let connect many circuits to one TTL output.

Propogation Delay

Every real device or circuit has a capability of storing charge in it. So there is always a delay while changing the signal from LOW to HIGH and from HIGH to LOW. In general every device needs a setup time and hold time to detect the change and respond it. However, this is not

next up previous contents
Next: 8086/8088 Microprocessor Up: CSE424 Microprocessors and Microcomputers Previous: Contents   Contents
Lokman 2003-06-17