Interrupt Handling

Interrupts

When interacting with IO devices that provide or require data at relatively low data transfer rates, the CPU time is wasted while waiting the IO device to be ready to send or receive next data.

To not waste time, a technique called interrupt processing has been developed. In this technique, CPU does not need yto check if the device is ready, but the devices inform the ready situation by interrupting the CPU.

For example, if a keyboard is connected to the system, as soon as a key is pressed, a signal interrupts the processor. The following shows a time line of a system where a typist typing data through a keyboard, a printer prints data and another program executing.

Interrupts can be classified into three groups:

External interrupt:

(Hardware interrupt) Hardware interrupts generated by external hardware such as keyboard, disk, serial port, ethernet etc.

Internal interrupt:

Hardware interrupts generated by CPU as a result of an errorenous condition(divide by zero, overflow, invalid opcode etc).

Software interrupt:

generated by interrupt instructions.

One problem with interrupt processing is to know the source of interrupt. For this reason every unique source of interrupt has a unique number called interrupt number or type.

Interrupts in 80x86

In 80x86 processors, an interrupt is either a hardware generated or software generated CALL. Either an hardware or software signal will interrupt the program by calling an Interrupt Service Procedure(ISP) or Interrupt Handler.

For hardware interrupt three pins are available: INTR(Interrupt), INTA'(Interrupt Acknowledgement) and NMI(Non Maskable Interrupt).

The following is the internal interrupts in 8086

Divide Error

(type 0)

Single Step or Trap

There are five interrupt instruction in the 80x86 CPU's.

INT n, INT 3, INTO, BOUND, IRET

Interrupt Vectors

An interrupt vector contains the address( segment and offset) of an ISP.

In real mode, an interrupt vector is a 4-byte far address stored in the first 1024 bytes of memory. For each interrupt type a vector is assigned, and there are 256 different vectors. I.e. there can be 256 unique source of interrupts in 80x86. The address of an interrupt vector is found as follows:

The address of vector n = n*4

Figure 28: Vector table

For example the vector address of 8 is 8*4=20h

Figure 29: Vector for interrupt 8

The first five interrupt types are used for internal or special interrupt sources.

Figure 30: Special vectors

In protected mode, the vector table is replaced by an interrupt descriptor table that uses 8-byte descriptors for each of the interrupts.

Intel reserves the first 32 interrupt vectors for internal interrupts. The rest is available to user.

Interrupt Operation

After the execution of each instruction, the microprocessor checks for an interrupt request according to the types in the following order.

1. internal interrupts
2. hardware interrupts
3. Software interrupts

Whenever an interrupt is encountered, CPU does the followings:

1. get or assign(for internal interrupts) the interrupt type n.
2. Push flags into the stack.
3. Clear T and I flag bits.
4. Push CS and IP to the stack.
5. Fetch new value of CS and IP as follows:

   CS $\leftarrow M[<vector-address>+2]$
   IP $\leftarrow M[<vector-address>]$
   $<vector-address>=n*4$

In fact an interrupt can be simulated by the following instructions:

PUSHF

CLI

CALL FAR PTR [n*4]

Example

Find the beginnning address of the ISP for interrupt 8.

First find the vector address for this interrupt. The vector address is $8*4=20h$. Therefore, the four bytes begginning from the address contains the beginning address of the ISP. Assume it contains the value 44325621h. Then the address of ISP is 2156h:3244h.

Interrupt Instructions

INT n

causes interrupt type n where n is between 0 and 255. The vector address of the type n interrupt is 4*n. For example, "INT 20" calls the ISP whose beginning address is stored in the location 20*4=80.

INT 3

one byte version of the INT n instruction where n is 3. Usually used for breakpoint implementation in debugging, because it is easy to insert a 1 byte instruction into a program.

INTO

This instruction checks the O(overflow) flag. If it is set, it invokes an INT 4. Otherwise, does nothing and the control is passed to the next instruction in sequence.

BOUND reg,mem

It compares a 16-bit or 32-bit register content against the contents of two words or doublewords of memory. If the register value is less than the first word/doubleword(lower boundary) or higher than the second word/doubleword(upper boundary), then a type 5 interrupt occurs. Otherwise, it does nothing.

For example, if the BOUND SI,DATA instruction executes, then the word M[DS:DATA] contains the lower boundary and the word M[DS:DATA+2] contains the upper boundary.

Example Program

The following program is an initializer and interrupt handler for the interrupt 9(keyboard interrupt in PC)

stack segment
 st dw 256 dup(?)
stack ends
data segment
  oldsr dd ?
  oldss dw ?
  oldsp dw ?
data ends
code segment
   .386
assume cs:code,ds:data
main:
    mov ax,data
    mov ds,ax
    mov ax,0
    mov es,ax
;store old interrupt number
    mov bx,9
    shl bx,2    ;multiply by 4 and get vector number
    mov ecx,es:[bx]
    mov oldisr, ecx   ;store old vector 
;put new interrupt number
    mov cx,offset myisr-for-int9
    mov es:[bx],cx       ;store offset address of new isr
    mov ax,cs
    mov es:[bx+2],ax     ; store segment address of new isr
; stay resident
    mov ax,3100h
    mov dx,100        ;reserve sufficient amount of memory for this program to be resident
    int 21h           ; return to dos but this program will stay resident


myisr-for-int9:
     ; set SS and SP, if you want to use your stack segment
     push ax      ; ax is modified, so save
     push ds      ; ds is to be modified, so save it
     mov ax,data
     mov ds,ax     ; ds now points to our data segment
     mov oldss,ss  ; save old ss
     mov ax,stack
     mov ss,ax         ; ss now points to our stack segment
     mov oldsp,sp  ; save old sp 
     mov sp,offset st 
     add sp,256    ; set sp to top of stack

   ; call old ISR
     pushf
     call far ptr oldisr      ; simulate an interrupt
   ;do what you want
      .
      .
     mov sp,oldsp
     mov ax,oldss
     mov ss,ax
     pop ds
     pop ax
     iret
     
code ends
end main

Hardware Interrupts

The INT signal of the microprocessor is used to request interrupt. This signal can be maskable by the I flag.

The problem in the hardware interrupt is to get the interrupt type.

One Device-One Vector case

When device A requested an interrupt it sets the IR flag in it and thus raises the INT line of the bus master. When bus master recognizes the interrupt, it issues an interrupt acknowledgement cycle to read the interrupt vector.In this figure, a three state buffer puts the vector 0Fh to the data bus when the INTA' signal is activated. Then bus master begins to run the ISP associated with this vector.

The IR flag in the device A must be cleared after the interrupt recognized. Otherwise it will continue to give the interrupt. There may be many methods to achieve this.

Method 1

The INTA' line is directly connected to the IR flag or device A to clear it.

Method 2

IR flag can be cleared by writing to a port in the device A. In Intel family of processors, at the beginning of ISP, the interrupt is disabled. So in the ISP, the IR flag must be cleared before enabling the interrupts.

Multiple Device-Single Vector Case

Figure 31:

Since there is only one INT line, there are two problems that must be solved by the bus master:

• Which device has request an interrupt?
• If more than one device request an interrupt, which one will be served first?

The first problem can be solved with a technique known as polling. The CPU can read the value of the IR flag in each device via an input port. So at the beginning of ISP the following algorithm is used.

1. N$\leftarrow$ 0
2. Read IR of Device with number N.
3. If it is 1 then jump to the associated ISP of this device. Otherwise continue.
4. Increment N.
5. jump to step 2

By this way the second problem can also be solved. Poll the devices according to an order. Then the device first polled will be serviced first.

Multiple Device-Multiple Vector Case

In this case, assume a unique vector is assigned to every interrupting device. Then the problem to be solved is the handling of simultaneous interrupts.

The following circuit shows a solution.

For each combination of request a new interrupt vector is generated.

The disadvantage of this method is that the maximum number of interrupt source is 8.

Figure 32:

Priority Encoding

Figure 33: An 8-bit parallel priority encoder

Daisy Chaining

In daisy chained interrupt structures, the priority among the devices are resolved in a serial fashion.

If din=0 and irq=1 then dout=1
If din=0 and irq=0 then dout=0
If din=1 then dout=1.

In this scheme, only one device releases its vector on the bus during an interrupt acknowledge.

Figure 34: Daisy Chain structure

Nonmaskable Interrupt

This is an edge-triggered signal that requests an interrupt on the rising edge. After the rising edge, NMI must remain a logic 1 until it is recognized by the microprocessor. Before the rising edge is recognized, the NMI pin must be a logic 0 for at least two clocking period(setup time=2 clock pulse, hold time=until recognized).

As the name implies, it is not maskable. I.e. can not be disabled. So it is often used for parity errors and other major system faults such as power failures. The following is a sample power failure detection circuit.

Question: Why the NMI interrupt signal recognized on the rising edge, although INT signal is a level detected signal.

8259A Programmable Interrupt Controller

Pins

Connecting

The following figure shows a 8259 decoded at port 0400H and 0402H.

Operation

Each interrupt input has a mask bit and an in-service bit. If the mask bit of an input is set, then it is disabled. The mask bits can be set or reset by the programmer. The in-service bit of an interrupt input is set whenever an interrupt from this input is accepted. The in-service bit is cleared by an EOI(End of Interrupt) command.

When the chip gets an interrupt in one of its or more than one input do the followings:

• The chip considers only the inputs which are not masked and resolve the priority among them. Initially, the IRQ0 has highest and IRQ7 has lowest priority. The priority can be modified by EOI commands. While resolving the priority it also considers in-service bits. If the in-service bit of the interrupt is already set, then this interrupt is not allowed. Then 8259 selects an allowable input which has the highest priority
• It requests an interrupt to the bus master via INT line. If INTA' is activated by the master, then it releases the corresponding interrupt vector to the data bus and set its corresponding in-service bit. The interrupt vector is base vector+IRQ number. For example for IRQ4, the vector is base vector+4.The base vector is written to the 8259 via ICW2 by the master( in PC AT systems the base vector is 8).
• The in-service bit of an interrupt is cleared by an EOI command. This command can be given automatically by the 8259 or by software. This is usually done at the end of ISP.

Programming

Initialization Command Words

There are four initialization command words for the 8259 that are selected when the $A_0$ pin is a logic 1. There are two ways of initialization:

send ICW1,ICW2,ICW3 in the order

send ICW1,ICW2,ICW3,ICW4 in the order.

The second way is used if more than one 8259 are used in cascade mode.

Operation Command Words

OCW1,OCW2 and OCW3 are used to direct the operation of the 8259A after it is initialized. OCW1 is selected when $A_0=1$. OCW2 is selected when $A_0=0$, $D_4=0$ and $D_3=0$. OCW3 is selected when $A_0=0$, $D_7=0$, $D_4=0$ and $D_3=1$. The following is an explanation of each words.

OCW1

This is interrupt mask register used to set and read the mask bits . When a mask bit is set, it will mask (turn off) the corresponding interrupt input. The mask register is read when OCW1 is read.

OCW2

OCW3

The various values causes various actions.

$\begin{array}{cccccccccp{3cm}} A_0 & D_7 & D_6 & D_5 & D_4 & D_3 & D_2 & D_1 & D_0 \hline 0 & 0 &ESMM & SMM &0 & 1& P & RR & RIS \hline \end{array}$

00xx011xx

get the poll command word on the next read of OCW3.

00xx01010

get the IR (interrupt request) register on the next read of OCW3.

00xx01011

get the IS(in-service) register on the next read of OCW3.

Example

Assume a keyboard is connected to the IR2 line of a 8259 located at 300h. Write an initialization and ISP for this such that the interrupt vector of the keyboard is 56h and the keyboard port is at 600h.

Cascoding 8259

When a slave gives an interrupt, the master informs the slave by CAS3-CAS0 signals to release its vector. If a slave is connected to IRn input of the master, then the slave's id must be n.