Basic IO Interface

Introduction

IO ports and IO devices are the ports of interaction of a computer with its environment or physical events. In each IO device there are one or more ports. Each port has a unique address.

Isolated and Memory Mapped IO

There are two completely different methods of interfacing IO to the microprocessor: isolated IO and memory mapped IO.

Memory Mapped IO

In memory mapped IO, the IO ports are treated as a memory location. I.e. some memory locations are dedicated to the IO ports. The advantage of this method is that to access ports, no additional instructions are required and the number of signals from the microprocessor is reduced.

Motorola type of microprocessors uses this method to connect and address the IO ports.

Isolated IO

In isolated IO the memory address and IO port address are seperated. For this seperation, additional information must be provided by the microprocessor.In every microprocessor utilizing this method, the address lines for memory and IO ports are the same. However, a seperate signal indicates whether the address on the address lines belongs to memory or ports. The advantage of this method is that all the memory address space can be dedicated to the memory.

The 80x86 devices uses this method to interface and address IO ports. However, the firts method can still be used. Since the IO address space is different, it uses seperate instructions to access to the IO ports. These are IN and OUT instruction. In 8086 8-bit and 16 bit ports are available, so IN and OUT instructions can read/write 8-bit and 16 bit data. The maximum number of ports is 64K. Thus the port addresses uses only the lower 16 bits of the adress signals.

The System Bus Used

In the subsequent lectures we will use the system bus whose signals are described below:

System Bus Signals

Address/data
A19-A0	address bus	Bidirectional, 3-state
D15-D0	data bus	Bidirectional, 3-state
Handshaking for data read/write
RD'	read from memory/IO	output,3-state
READY	ready signal	input
M/IO'	select memory or IO	output,3-state
WR'	Write to memory/IO	output,3-state
ALE	Address latch enable	output
BHE'	bus high enable	output
Interrupt signals
INTR	interrupt request	input
NMI	non-maskable interrupt	input
RESET	reset	input
INTA'	interrupt acknowledge	output

Basic Input and Output Interfaces

A port can be seen as a register/buffer in an IO device. A port is either an output port or input port. However, both an input port and output port can be assigned to the same address. More than one output port can be assýgned to the same address, but more than one input port can not be assigned to the same address(why?).

Similar to the memory, the IO address space is seperated into two banks: high bank and low bank. Thus it is possible read 16 bits at once instead of doing the job in two subsequent read/write.

The BHE' and A0 signals are used to read/write 8-bit and 16 bit data from/to ports.

BHE=0 Enable high bank

A0=0 Enable low bank

BHE'	A0
0	0	Read/write data through both bank
0	1	Read/write data through high bank
1	0	Read/write data through low bank
1	1	No read/write

Basic Input Port

When IN AL,DX instruction is executed, the content of DX is put to the address bus and a read cycle on the bus is issued. The only difference between and IO read/write cycle and memory read/write cycle is the value of the IO/M' signal. The following illustrates an input port using 74LS244 three state buffer.

Since this port has a specific address, there must be a circutry that enables the three state buffers when this address matches. This is called address decoding or address matching circuit.

Basic Output Port

Basic Input/Output Ports with Odd Addresses

16-bit Port Address Decoding

However, unlike the memory read, in an IO read, reading a port can cause an event to occur in an IO device. So if this happens, for 8-bit read, the control signals for each bank must be seperated. The following figure illustrates an 16 bit input port

Address Decoding Circuits

Simple gate decoder

Using Decoder IC's

If multiple ports are assigned subsequent addresses, then usually Decoder IC's are used for this purpose. For example assume there are four

8255 The Programmable Peripheral Interface

This is a single chip provides three 8-bit programmable port(i.e. the configuration of the ports can be changed).

For the 8255 to be read or written, CS' input must be activated. The following is the explanations of some functions.

RESET	CS'	A1	A0	Explanation
0	1	x	x	Not selected
0	0	0	0	Port A is read or written(determined by content of the RD' and WR' signals
0	0	0	1	Port B is read or written
0	0	0	1	Port C is read or written
0	0	0	1	Command register is read or written
1	x	x	x	The chip is reset

When the chip is reset, all ports becomes simple input ports using mode 0 operations.

Interfacing

Programming

The 8255 is programmed through command register. There are two group of registers: Group A(PA0-PA7,PC4-PC7) and the group B(PB0-PB7,PC0-PC3).

Group A and Group B pins are programmed by writing a command byte A to the command register. The format of command byte A is given is the following.

Group A pins are programmed as either input or output pins. They can operate in modes 0,1 or 2. Group B pins are also programmed as either input or output pins. It can operate in either mode 0 or mode 1.

Another group of commands known as command byte B is used to set/reset the individual bits of the port C. Its format is the following.

Mode 0 operation

It allows the 8255 ports to function either as a buffered input or as a latched output. These are the same as the basic input and output circuits discussed.

As an example assume there are 8 keys and 8 LEDs connected to the port A and port B of an 8255 whose port address is as follows:

Port	Address
A	4730h
B	4732h
C	4734h
command	4736h

The aim is to light $LED_n$ when the $SW_n$ is closed.

Mode 1 operation

Strobed Input

Explanation of operations:

1. When STB' input becomes 0, the data available in port A inputs are accepted by the 8255 and IBF output becomes 1.
2. When STB' becomes 1, the data is no longer accepted and thus the data during STB'=0 will be kept in the internal latch of the port A. After STB' becomes 0, i.e. after the raising edge, if the interrupt is enabled, the INTR pin becomes 1. If this signal is connected to the CPU it indicates an interrupt.
3. If the port A of the 8255 is read by a bus master,e.g. CPU, then it is assumed the buffer is emptied and IBF signal becomes low to indicate this. Also INT signal becomes low, if it was high, because the request is serviced and no longer necessary.

Note that the values on all of these signals can be read by the CPU by reading the corresponding bits of port C.

Example:

Strobed Output

1. When a data is written to the port A by the bus master, the OBF'(Output buffer full) signal becomes 0 to indicate this to the connected device.
2. When the connected device accepts data, it responds by dropping the ACK' signal to 0. Then 8255 accepts that the data buffer is read and assume it is empty. So it raises the OBF' signal to indicate that the data buffer is empty now. It also raises the INT signal, if the interrupt is enabled, to request an interrupt. If this signal is connected to the bus master, then it informs the bus master that the buffer is empty and should be filled with data.
3. If the bus master somehow write a data to the port A buffer, the INT signal becomes low, if it was high, because the request is serviced and no longer necessary.

Example:

Mode 2 operation

It is a combination of mode 1 strobed input and buffered output. However, there are differences such as the function of the ACK signal changes.