Thesis submitted to WARF
Interconnect Dominant
Design Methodology
for DSP architectures
- A Mixed Number System
based Approach
With
deep submicron (DSM), the gates have become smaller and faster, whereas the
amount of interconnect on a chip used to connect these small and fast gates has
grown exponentially. The ratio of interconnect delay to gate delay continues to
increase in favor of interconnect delay as DSM designs continue to get smaller.
The result is a shift in the design paradigm based on interconnect delay
dominance.
Buffer insertion
techniques have been successful in reducing interconnect delay. This consumes
power and occupies a large amount of the chip area. The power consumed by these
delay optimal devices and wires will increase as we go into the DSM era. This
thesis investigates the DSM issues in the design of DSP algorithms and
architectures. The DSM issues have been analyzed in great depth with respect to
interconnect dominance in FFT algorithms and architectures, as well as in DFT.
One of the main findings of the thesis is that the FFT architectures suffer
from high degree of interconnect dominance making them unsuitable for DSM
technology when compared with DFT.
High
performance, accuracy and low power are the most important design parameters of
DSP architectures. In DSM based technology, while high performance can be
achieved, power becomes a critical factor, which needs either a new
architecture or even a new number representation. The computational complexity
of DSP algorithms leads to high power consumption particularly in high
performance applications. An architecture for Arithmetic Processor based on a
mixed number representation is presented. Here, the sign/log number system is
embedded into the residue number system. It is shown
that this mixed number representation called Logarithmic Residue Number System (LRNS) achieves low power and high performance over the Binary, Residue and sign/log number systems. It is further shown that unlike the sign/log number system, LRNS maintains an accuracy of within 1 percent of the binary number system. A special purpose power efficient instruction set for the processor is proposed.
The
work presented in this thesis is expected to help in developing high performance
low power DSP systems. As a case study, LRNS is shown to reduce the
computational complexity in time frequency transforms like the Gabor.
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