Subramanian Rama

                                     e-mail: subramanianr82@yahoo.co.in

                                            url: www.subramanian.cjb.net

           

College Address                                                                Residential Address

Final Year B.E.,                                                                  ‘SRI RAMS’, Flat No.6

Dept of Electronics & Communication                                  Old No.22, New No.19

S.S.N College of Engineering                                               Pey Alwar Koil Street

(University of Madras)                                                         Triplicane

Kalavakkam 603 110                                                          Chennai 600005

Tamil Nadu                                                                         Tamil Nadu

INDIA                                                                                INDIA

Ph. 91- 4114- 475063 / 64 / 65                                          Ph. 91- 044- 28445736 / 28445004

 

 

 


PROFILE

 

A highly motivated, team-oriented individual possessing leadership qualities and problem solving skills, with good research experience in a number of fields as well as a good command over English in both written and spoken.

 

OBJECTIVE

 

Aiming to become a researcher cum academician and experiment my own thoughts and ideas in my research to reach great heights

 

EDUCATION                   SSN College of Engineering

                                           B.E. in Electronics and Communication (Final Year)

                                           Aggregate     77.1% (upto 7th Semester)

                                                                   

LANGUAGE PROFICIENCY

 

English, French, Hindi and Tamil

 

ACADEMIC HIGHLIGHTS

 

ENTRANCE EXAMINATION FOR B.E DEGREE PROGRAM (Conducted by the Goverment of TamilNadu, India)

 

Marks obtained 264.78 out of 300

Awarded Free Merit Seat in Undergraduate Engineering at SSN College of Engineering

 

UNDERGRADUATE EDUCATION - COURSES IN MAJOR

 

Semester III

Course                                                            Score %              

Engineering Electromagnetics                             85                                                      

Electrical Engineering                                        93           (Class First)             

Electrical Circuits and Machinery Lab                92                    

Electronics Lab I                                              87

 

 

 

 

 

 

Semester IV

Course                                                            Score %         

Transmission Lines and Wave Guides                 92           (Class First)

Solid State Circuits – I                                       81                  

Mathematics IV                                                 98           (College Second)

Electronics Lab II                                              90

Computer Laboratory                                        94

 

Semester V

Course                                                            Score %       

Numerical Methods                                           84                

Digital Signal Processing                                    87           (Class Second)

Integrated Circuits Lab                                      90                    

Electronics Lab III                                             88

 

Semester VI

Course                                                            Score %              

Probability theory and Random Process             87          

Antennas and Propagation                                 85           (Class Second)

Microprocessor lab –I                                       92                  

 

 

Mathematics Courses taken during my undergraduate Education

 

Course                                                            Score %              

Mathematics I                                                    88

Mathematics IV                                                 98           (College Second)

Numerical Methods                                           84                

Probability theory and Random Process             87          

 

PROFESSIONAL MEMBERSHIPS

 

· IEEE student member      

· ACM student member  

· Member of the IEEE Communications Society (ComSoc)

 

FELLOWSHIP AWARDS

 

I was awarded scholarship for attending the International Conference on High-Performance Computing (HiPC 2002), co-sponsored by the IEEE Computer Society & ACM SIGARCH, held at Bangalore, India from the 18th to the 21st of December 2002

 

INDUSTRIAL INTERNSHIP

 

Underwent internship in MELS INDIA Limited (a leading industry that manufactures back driver boards and Fault testing boards for military purposes) under the following departments

 

TECHNICAL & CODING EXPERIENCE

 

               Operating Systems: Microsoft Windows’ 95/98/NT, Linux, MS-DOS

 

               Languages             : BASIC, FORTRAN, C, C++, Java, Visual Basic,

                                                HDL Verilog

q       Had the experience of coding in C and C++ as a part of my undergraduate college curriculum and also during my period of research at WARF in DSP related algorithms

q       Developed an online quiz software in Visual Basic for my department symposium during my undergraduation

q       Currently doing part of the simulation work of my project in HDL Verilog

 

         Databases             : FoxPro, Microsoft Access, Oracle

 

q       Used Microsoft Access as the Database for the Online Quiz Software I developed

     

                Packages               : Adobe PageMaker, Matlab, TEX

 

q       Had the experience of designing my department Magazine ‘ESSENCE’ using Adobe PageMaker

q       Had the experience of solving matrix related problems and doing simulations for my research work at WARF in Matlab

q       Did my thesis in TEX

 

RESEARCH HIGHLIGHTS

 

Research Interests

 

 

RESEARCH TRAINING PROGRAM

 

I have joined a 24-month (Part-time) Research Training Program (RTP) at Waran Research Foundation (WARF) to specialize in the above areas.

 

WARF is running a part time Research Training Program (RTP) for highly motivated undergraduate students who are aspiring for a research career. The duration of the program is 24 months. The RTP is composed of regular classroom lectures (in the areas listed below), discussion on research reprints and initiating the students in various research areas. These discussions help train the students onto the methodology of research paper analysis. As a part of the RTP the students based on their research work carried at WARF try to publish in leading IEEE journals and International conferences.

 

Admission criteria

 

WARF admits students of Computer Science Engineering and Electronics and Communication Engineering departments from 5th semester, from reputed institutions. The selection process is based on several levels of interview and discussions with the Head of WARF.

 

COURSE PROGRAM AT WARF

 

· Advanced computer architecture

· Advanced Algorithms

· VLSI architecture

· Design For Testability for DSM & GHz Technology

· Graph Theoretic Algorithms

· VLSI Physical Design Algorithms in the context of DSM & GHz Technology

· Advanced FSM design

· Stochastic processes and probability theory

 

THESIS WORK AT WARF

 

Based on the work carried out at WARF, a Research Thesis submission at the end of the program is mandatory. The Thesis will be a compilation of the research work carried out at WARF.

 

RESEARCH PUBLICATIONS

 

ü      I have presented a Paper titled ‘An Embedded Memory Based Self Iterating FFT      

            Processor with reduced Area and Computational Complexity’ at VISION 2002, A        

            National Level Technical Symposium organized by Anna University, Chennai, 

            INDIA

 

Papers Presented

 

“ An Embedded Memory based Self Iterating FFT processor with reduced area   

   and computational complexity”

 

Abstract --- In this paper we discuss the design and implementation of a FFT processor, which uses 2’s complement Imaginary Radix Number system representation to reduce the number of effective multiplications per butterfly to one, which in a conventional processor are four. The FFT processor, which we propose is a highly structured single stage self-Iterating processor. The FFT processor utilizes an Embedded Memory for compensating any increase in time caused by the semi-parallel approach. Such area-time performance makes the proposed design rather attractive for use in long-length DFT applications.

 

Papers accepted for presentation and publication

 

ü      The following two papers have been accepted for presentation and publication at the International Signal Processing Conference (ISPC) and Global Signal Processing Expo (GSPx), Dallas, Texas, USA

                  

·        “Emergent Impact of DSM technology on DFT and FFT architectures”  

 

Abstract --- This paper begins to explore the interconnect and power dominance in the Fast Fourier Transform (FFT) architectures under Deep Sub Micron (DSM) technology. Most of the architectures proposed for FFT considers only the functional count ignoring the passive (interconnect) area. In this paper we analyze the interconnect complexity of the basic FFT algorithm for different radices and sample points (problem size) and find that inspite of the increased hardware complexity within the Computational elements (CE) higher radix proves to be more efficient than lower radix from the interconnect point of view. The analysis has also been extended to multidimensional FFT architectures. The paper also highlights the considerable amount of power consumed by the transitions in the lengthy registers in the Delay Commutators (DC) employed in FFT architectures. Compared with the pipelined matrix-column vector multiplication architecture for Discrete Fourier Transform  (DFT), the multi-dimensional FFT architecture is found to suffer from increased latency and power due to the Delay Commutator (DC) circuit apart from the increased interconnect complexity and a comparative analysis of power, Interconnect and performance is made between the conventional matrix-column vector architecture for DFT and FFT is made and the results of the analysis show that the conventional matrix-column vector based DFT suits DSM technology over FFT because of the substantial reduction of Interconnects, power and latency in the former.

 

·        “ A Mixed Number System Based Low power, High performance Arithmetic Processor for DSP applications”

 

Abstract --- In Deep Sub Micron (DSM) based technology, while high performance can be achieved power becomes a critical factor, which needs either a new architecture or even a new number system. The focus of this paper is present architecture for an Arithmetic Processor based on mixed number system to achieve low power and improved accuracy without sacrificing on performance in the context of DSM technology. Using Residue Number System (RNS) and Sign Logarithmic Number System (LNS), a number of Digital Signal Processing (DSP) related architectures have been proposed. The merits and demerits of these number systems are analyzed in the context of power, performance and accuracy leading to a new approach for arithmetic operations by embedding the LNS into the RNS and a new mixed number system namely the Logarithmic Residue Number System (LRNS) is evolved. Such a mixed number system namely the LRNS will give better performance, lower power consumption and improved accuracy. The proposed LRNS based arithmetic processor is expected to fill the gap between the conventional architectures and the DSM technology, achieving reduced interconnect complexity and low power without sacrificing on performance and attaining better accuracy.

 

Papers under communication

·        Analysis of Interconnect Complexities in DSP Architectures

Abstract --- In the context of Deep Sub-Micron (DSM) technology, several critical design parameters such as performance, power, noise immunity etc. are strongly influenced by interconnects. Scaling into the DSM technology has shifted the focus from device dominated to interconnect-dominated device methodologies. Further, the interconnect delay dominates over the gate delay. The interconnect capacitance becomes comparable or even larger than the gate capacitance. Thus, for dynamic logic the charge of interconnects may overwrite the content of the gate capacitance. The vast increase in the number of interconnects has made the interconnect capacitance the cause of most of the on chip power dissipation. Power efficient architectures are being proposed by many to tackle this critical design parameter under DSM technology. In this paper the interconnect complexities of DSP Architectures like the FFT are analyzed.

 

Papers under preparation

 

·        “Reconfigurable Butterfly Arrays for Low Power DFT and FFT Architectures”

 

Abstract --- It is often desirable in modern signal processing applications to perform Fast Fourier Transform (FFT) for very large values of radix. In this paper a reconfigurable low power butterfly processing element (PE) for calculation of radix r FFT is being proposed. In the butterfly array the DFT calculations are being performed as an inner product. This butterfly array reconfigures itself for different radix so as to optimize on power and performance. The proposed reconfigurable butterfly array also takes advantage of the redundancy within the butterfly. The proposed butterfly array tunes itself between different number systems viz. the Binary Number System, Residue Number System and the Logarithmic Number System hence arriving at a trade of between the merits and demerits of the different number systems to provide the best optimization on power, performance and accuracy.

 

CO-CURRICULAR AND EXTRACURRICULAR ACHIEVEMENTS

 

 

 

SPECIAL POSITIONS HELD DURING UNDERGRADUATE COURSE