RESEARCH PUBLICATIONS
ü
I have presented a Paper
titled ‘An Embedded Memory Based Self Iterating FFT
Processor with reduced Area and Computational
Complexity’ at VISION 2002, A
National Level Technical Symposium organized by Anna
University, Chennai,
INDIA
“ An Embedded Memory based Self Iterating FFT processor with
reduced area
and computational
complexity”
Abstract --- In this paper
we discuss the design and implementation of a FFT processor, which uses 2’s
complement Imaginary Radix Number system representation to reduce the number of
effective multiplications per butterfly to one, which in a conventional
processor are four. The FFT processor, which we propose is a highly structured
single stage self-Iterating processor. The FFT processor utilizes an Embedded
Memory for compensating any increase in time caused by the semi-parallel
approach. Such area-time performance makes the proposed design rather
attractive for use in long-length DFT applications.
Papers
accepted for presentation and publication
ü The following two papers have been accepted for
presentation and publication at the International Signal Processing
Conference (ISPC) and Global Signal Processing Expo (GSPx), Dallas, Texas, USA
·
“Emergent
Impact of DSM technology on DFT and FFT architectures”
Abstract --- This paper begins to explore
the interconnect and power dominance in the Fast Fourier Transform (FFT)
architectures under Deep Sub Micron (DSM) technology. Most of the architectures
proposed for FFT considers only the functional count ignoring the passive
(interconnect) area. In this paper we analyze the interconnect complexity of
the basic FFT algorithm for different radices and sample points (problem size)
and find that inspite of the increased hardware complexity within the
Computational elements (CE) higher radix proves to be more efficient than lower
radix from the interconnect point of view. The analysis has also been extended
to multidimensional FFT architectures. The paper also highlights the
considerable amount of power consumed by the transitions in the lengthy
registers in the Delay Commutators (DC) employed in FFT architectures. Compared with the pipelined
matrix-column vector multiplication architecture for Discrete Fourier Transform (DFT), the
multi-dimensional FFT architecture is found to suffer from increased latency
and power due to the Delay Commutator (DC) circuit apart from the increased
interconnect complexity and a comparative
analysis of power, Interconnect and performance is made between the
conventional matrix-column vector architecture for DFT and FFT is made and the
results of the analysis show that the conventional matrix-column vector based
DFT suits DSM technology over FFT because of the substantial reduction of
Interconnects, power and latency in the former.
A copy the
above paper is available in pdf format at the following link for download.
Right click and save the file or click to open the file
·
“ A Mixed Number
System Based Low power, High performance Arithmetic Processor for DSP
applications”
Abstract --- In Deep Sub Micron
(DSM) based technology, while high performance can be achieved power becomes a
critical factor, which needs either a new architecture or even a new number
system. The focus of this paper is present architecture for an Arithmetic
Processor based on mixed number system to achieve low power and improved
accuracy without sacrificing on performance in the context of DSM technology. Using Residue Number System (RNS)
and Sign Logarithmic Number System (LNS), a number of Digital Signal Processing
(DSP) related architectures have been proposed. The merits and demerits of
these number systems are analyzed in the context of power, performance and
accuracy leading to a new approach for arithmetic operations by embedding the
LNS into the RNS and a new mixed number system namely the Logarithmic Residue
Number System (LRNS) is evolved. Such a mixed number system namely the LRNS
will give better performance, lower power consumption and improved accuracy.
The proposed LRNS based arithmetic processor is expected to fill the gap
between the conventional architectures and the DSM technology, achieving
reduced interconnect complexity and low power without sacrificing on
performance and attaining better accuracy.
A copy the
above paper is available in pdf format at the following link for download.
Right click and save the file or click to open the file
Papers under communication
·
Analysis of Interconnect Complexities in DSP Architectures
Abstract --- In the context of Deep Sub-Micron (DSM) technology,
several critical design parameters such as performance, power, noise immunity
etc. are strongly influenced by interconnects. Scaling into the DSM technology
has shifted the focus from device dominated to interconnect-dominated device
methodologies. Further, the interconnect delay dominates over the gate delay.
The interconnect capacitance becomes comparable or even larger than the gate
capacitance. Thus, for dynamic logic the charge of interconnects may overwrite
the content of the gate capacitance. The vast increase in the number of
interconnects has made the interconnect capacitance the cause of most of the on
chip power dissipation. Power efficient architectures are being proposed by
many to tackle this critical design parameter under DSM technology. In this
paper the interconnect complexities of DSP Architectures like the FFT are
analyzed.
Papers under preparation
·
“Reconfigurable Butterfly Arrays for Low Power DFT and FFT
Architectures”
Abstract --- It is often
desirable in modern signal processing applications to perform Fast Fourier
Transform (FFT) for very large values of radix. In this paper a
reconfigurable low power butterfly processing element (PE) for calculation of
radix r FFT is being proposed. In the butterfly array the DFT calculations are
being performed as an inner product. This butterfly array reconfigures itself
for different radix so as to optimize on power and performance. The proposed
reconfigurable butterfly array also takes advantage of the redundancy within
the butterfly. The proposed butterfly array tunes itself between different
number systems viz. the Binary Number System, Residue Number System and the Logarithmic
Number System hence arriving at a trade of between the merits and demerits of
the different number systems to provide the best optimization on power,
performance and accuracy.