Mr. Jatindra Kumar Deka
Assistant Professor, C. Sc. & Engg. Dept.
Jorhat Engineering College, Jorhat Send Mail
EDUCATION:
Ph. D. (Computer Science and Engineering), I.I.T., Kharagpur, 2001.
M. Tech. (Computer Science and Information Technology), I.I.T., Kharagpur, 1993.
B. E. (Electronics Engineering), Motilal Nehru Regional Engineering College, Allahabad, 1988.
AFFILIATION:
Life Member of Indian Society for Technical Education (ISTE).
Member of IEEE.
Member of Indian Association for Research in Computing Science (IARCS).
RESEARCH INTEREST:
Artificial Intelligence,
CAD for VLSI,
Formal Verification,
Logic Programming.
PUBLICATIONS:
An Efficiently Checkable Subset of TCTL for Formal Verification of
Transition Systems with Delays. In Proceedings of 12th International Conference of VLSI Design '99,
Goa, India, Pages 294-299, 7-10 January 1999.
Reachability Analysis of Cellular Automata In 1999 Pacific Rim International Symposium on Dependable Computing
(PRDC 1999)
Model Checking on Timed Event Structures. IEEE Transactions on Computer Aided Design of Integrated Circuits and
Systems, Volume 19, Number 5, Pages 601-611, May 2000.
A Comparative Analysis of BDD-based and RULE-based Reachability
Problems for Cellular Automata. In Proceedings of International Conference of Computer Communication and
Devices 2000, I.I.T., Kharagpur, India, Pages 76-79(Vol-I), 14-16
December 2000.
Min-max Computation Tree Logic. Artificial Intelligence, 127(2001), Pages 137-162, March 2001.
Abstractions for Model Checking of Event Timings. In Proceedings of IEEE International Symposium on Circuits and Systems,
Sydney, Australia, Pages 125-128(Vol-V), 6-9 May 2001.
Ph. D. Thesis: Model Checking Techniques for
Reasoning about Events and Extremal Properties of Timed Systems.
