Texas Instruments TLC549 8-bit Analog-to-Digital Converter

Texas Instruments TLC549
8-bit Analog-to-Digital Converter

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Description

The TLC549 is a CMOS analog-to-digital converter integrated circuit built around an 8-bit switched-capacitor successive-approximation ADC. It is designed for serial interface with a micro-processor or peripheral through a 3-state data output and an analog input. The TLC549 uses only the input/output clock (I/O CLOCK) input along with the chip select (CS) input for data control. The maximum I/O CLOCK input frequency is specified up to 1.1 MHz.

The TLC549 provides an on-chip system clock that operates typically at 4 MHz and requires no external components. The on-chip system clock allows internal device operation to proceed independently of serial input/output data timing and permits manipulation of the TLC549 as desired for a wide range of software and hardware requirements. The I/O CLOCK together with the internal system clock allow high-speed data transfer and conversion rates of 40,000 conversions per second.

Functional Block Diagram

Operating Sequence

Notes:

The conversion cycle, which requires 36 internal system clock periods (17 ms maximum), is initiated with the eighth I/O clock pulse trailing edge after CS goes low for the channel whose address exists in memory at the time.
The most significant bit (A7) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits (A6 - A0) will be clocked out on the first seven I/O clock falling edges. B7 - B0 will follow in the same manner.

Recommended Operating Conditions
	Min	Nominal	Max	Unit
Supply Voltage, V_CC	3	5	6	V
Positive reference voltage, V_ref+ (see Note 3)	2.5	V_CC	V_CC+0.1	V
Negative reference voltage, V_ref- (see Note 3)	-0.1	0	2.5	V
Differential reference voltage, V_ref+, V_ref- (see Note 3)	1	V_CC	V_CC+0.2	V
Analog input voltage (see Note 3)	0		V_CC	V
High-level control input voltage, V_IH	2			V
Low-level control input voltage, V_IL	0		0.8	V
Input/Output clock frequency, f_clock(I/O)	0		1.1	MHz
Input/Output clock high, t_wH(I/O)	404			ns
Input/Output clock low, t_wL(I/O)	404			ns
Input/Output clock transition time, t_t(I/O) (see Note 4)			100	ns
Duration of CS input high state during conversion, t_wH(CS)	17			µs
Setup time, CS low before first I/O CLOCK, t_su(CS) (see Note 5)	1.4			µs
Conversion time, t_conv		12	17	µs
Output enable time, t_en			1.4	µs
Output disable time, t_dis			150	ns

Notes:

Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that applied to REF- convert to all zeros (00000000). For proper operation, the positive reference voltage V_ref+, must be at least one Volt greater than the negative reference voltage V_ref-. In addition, unadjusted errors may increase as the differential reference voltage V_ref+ - V_ref- falls below 4.75V.

This is the time required for the input/output clock input signal to fall from V_IHmin to V_ILmax or to rise from V_ILmax to V_IHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2ms for remote data acquisition applications in which the sensor and the ADC are placed several feet away from the controlling microprocessor.
To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and one falling edge of internal system clock after CS before responding to control input signals. This CS set-up time is give by the t_en and t_su(CS) specifications.

Principles of Operation

The TLC549 is a complete data acquisition system on a single chip. It contains an internal system clock, sample and hold, 8-bit A/D converter, data register, and control logic circuitry. For flexibility and access speed, there are two control inputs: I/O CLOCK and chip select (CS). These control inputs and a TTL-compatible 3-state output facilitate serial communications with a microprocessor or minicomputer. A conversion can be completed in 17µs or less while complete input-conversion-output cycles can be repeated in 25µs.

The internal system clock and I/O CLOCK are used independently and do not require any special speed or phase relationships between them. This independence simplifies the hardware and software control tasks for the device. Due to this independence and the internal generation of the system clock, the control hardware and software need only be concerned with reading the previous conversion result and starting the conversion by using the I/O clock. In this manner, the internal system clock drives the "conversion crunching" circuitry so that the control hardware and software need not be concerned with this task.

When CS is high, DATA OUT is in a high-impedance condition and I/O CLOCK is disabled.

The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain the conversion result. A normal control sequence is:

CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges and then a falling edge of the internal system clock after a CS before the transition is recognized. However, upon a CS rising edge, DATA OUT will go to a high-impedance state within the t_dis specification even though the rest of the integrated circuitry will not recognize the transition until the t_su(CS) specification has elapsed. This technique is used to protect the device against noise when used in a noisy environment. The most significant bit (MSB) of the previous conversion result will initially appear on DATA OUT when CS goes low.
The falling edges of the first four I/O CLOCK cycles shift out the second, third, fourth, and fifth most significant bits of the previous conversion result. The on-chip sample and hold begins sampling the analog input after the fourth high-to-low transition of I/O CLOCK. The sampling operation basically involves the charging of internal capacitors to the level of the analog input voltage.
Three more I/O CLOCK cycles are then applied to the I/O CLOCK terminal and the sixth, seventh, and eighth conversion bits are shifted out on the falling edges of these clock cycles.
The final, (the eighth), clock cycle is applied to I/O CLOCK. The on-chip sample and hold begins the hold function upon the high-to-low transition of this clock cycle. The hold function will continue for the next four internal system clock cycles, after which the holding function terminates and the conversion is performed during the next 32 system clock cycles, giving a total of 36 cycles. After the eighth I/O CLOCK cycle, CS must go high or the I/O clock must remain low for at least 36 internal system clock cycles to allow for the completion of the hold and conversion functions. CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise glitches on the I/O CLOCK line. If glitches occur on I/O CLOCK, the I/O sequence between the microprocessor/controller and the device will lose synchronization. If CS is taken high, it must remain high until the end of conversion. Otherwise, a valid high-to-low transition of CS will cause a reset condition, which will abort the conversion in progress.