If the mosfet capacitances alone gave a constant 6dB/octave fall in gain then the feedback loop gain would be 78dB at 5kHz and fall to unity gain at over 41MHz, as shown in black in the 2nd diagram. This gives a constant 90deg phase lag, but in reality there will be additional sources of phase shift, and to ensure unconditional stability we need to prevent the phase lag ever reaching 180deg before the loop gain falls to unity. The 1n input filter capacitor affects the loop gain, and with a low impedance signal source assumed there is a 6dB reduction in high frequency loop gain, above the audio frequency range, shown in red. The 390p capacitor from input to earth combined with the 10p across the overall feedback resistor maintain this gain reduction up to higher frequencies. The input complementary feedback pair (cfp) has a response -3dB around 5MHz, mostly because of the 300pF base-emitter capacitance of the pnp transistor at Ic = 12mA (mostly diffusion capacitance, which is proportional to emitter current), and consequently the loop response becomes as shown in blue, with unity gain at 8.4MHz. This may give an adequate phase margin if other sources of phase shift are negligible, but to take account of worst case component variations some further modification seems worthwhile.
A design exercise: think of 10 different ways to improve the phase margin - Here are 5:
(1). The input complementary feedback pair (cfp) -3dB frequency is determined partly by the gm of the npn transistor and Cbe of the pnp, and can be increased by reducing the 1k2 resistor to increase the npn transistor collector current, but this is already higher than the optimum value for low noise.
(2). The 1ohm emitter resistor could be increased. This has two effects, it reduces loop gain at all frequencies and also increases the -3dB frequency of the input cfp stage. The combination of two effects means that even a small change, from 1R to 1R5, can have a big effect on stability. Increasing this however increases closed-loop distortion at audio frequencies. The 0.006% 3rd harmonic at 20kHz would increase to 0.009%, which is still very good.
(3). The 220k overall feedback resistor with parallel 10p could have a 10k in parallel with 10p added in series. This would add a further 6dB step down in loop gain around 1MHz. This will increase closed loop gain a little above 1MHz, but there should be no serious problem.
(4). A similar step could be added by using a series resistor and capacitor connected across the 1k2 resistor in the cfp. 1n and 47R were tried with an earlier version, and seemed to work well, but coming out of positive clipping there was then a sharp notch, possibly caused by the 1n capacitor discharging during clipping and then needing to recharge.
(5). Increasing the 390p capacitor from input base to earth will also add a step down in gain, but this would be at too low a frequency, and add phase lag before the output inductor gave adequate protection against capacitive loads. The step from the 1n filter capacitor is already adding phase lag in a dangerous area, and more is quite definitely not needed. Any further added step should be at about 1MHz or higher.
The current favourite is the 1R5 emitter resistor, giving the result shown in green. The cfp -3dB frequency is now close to the loop unity gain frequency, giving a phase margin around 45deg. This is calculated, and includes a few approximations, but the measurements done so far seem to agree with the analysis in the sense that changes calculated to improve stability really do give improvements.